應用於60 GHz頻段功率分配器與合成器之研製

使用相位陣列 (phased array) 系統是未來通訊系統的趨勢，原因在於相位陣列系統具有可增加系統的訊號雜訊比值(signal-to-noise ratio, SNR)、有效等向輻射功率(equivalent isotropically radiated power, EIRP)以及空間干擾消除(spatial interference cancellation)等優點。而在相位陣列系統中，發射時需要將訊號平均的分配到不同的通道上，而在接收時需要將不同通道的訊號合併。因此在系統中需要一個功率分配器與功率合成器。在本論文中，我們使用互補式金屬氧化層半導體(CMOS)製程設計並實現了被動式功率分配器與合成器，以及主動式功率分配器。此論文分成五個章節，第一章會簡短介紹相位陣列系統。第二章則會介紹功率分配與合成器的基本原理以及在CMOS上的設計考量。在第三章中，分別設計了一個一對四的功率分配器，以及一個四對一的功率合成器。兩個電路都是使用台積電65奈米CMOS製成，操作頻率為60 GHz 頻段。此電路由Wilkinson 功率分配/合成器與緩衝放大器(Buffer Amplifier, BA)所組成。在此設計中，薄膜微帶傳輸線(thin-film microstrip line, TFMS line)被當作匹配元件，以減低基板損耗對電路的影響。一對四功率分配器的量測結果為：在頻寬為57到66 GHz下，一路小訊號增益為-0.9到3 dB，另一路小訊號增益為2.9到4.9 dB。隔離度最小為16.7 dB。最小的輸出功率1 dB壓縮點(OP1dB)是-3.67 dBm。而四合一功率合成器的量測結果為：在頻寬為57到66 GHz下，兩路的小訊號增益分別為4.9 到 11.2 dB，以及4.7到11.1 dB。隔離度最小為19.3 dB。最小的OP1dB是-4.83 dBm。造成模擬與量測之間差異的原因會在這部分做討論，並且會重新模擬電路。在第四章中，則是設計了一個操作在60 GHz頻段的主動式功率分配器；使用的是90奈米CMOS製程。此電路使用電流來分配功率。此電路設計具有寬頻的頻率響應以及小面積的優勢。量測結果顯示此電路當VDD偏壓在2 V時，兩路小訊號增益均大於0 dB且對稱。OP1dB則大於 -2.67 dBm。此電路架構是第一次在CMOS上被實現。第五章則會對整本論文做結論。論文中所呈現的三個電路都適用於未來相位陣列的應用，並且顯示出互補式金屬氧化層半導體製程於高頻應用的能力。

關鍵字

相位陣列；互補式金屬氧化層半導體；被動式功率分配與合成器；主動式功率合成器； 60 GHz應用

並列摘要

Using phased-array system is the trend of the future communication system, since phased array has benefit of improvement signal-to-noise ratio (SNR), improvement equivalent isotropically radiated power (EIRP), and spatial interference cancellation. The signal needs to be evenly split to each chain on transmitter and to be combined from each chain on receiver, since phased-array system is consisted of multiple transceivers and antennas. Therefore power splitter and combiner components are required. In this thesis, the passive power splitter, passive power combiner, and active power splitter are implemented by using complementary metal-oxide semiconductor (CMOS) process. The thesis is comprised of five chapters. The brief introduction of phased-array system is shown in chapter 1. The principle of power splitter and combiner, and design consideration on CMOS process are shown in chapter 2. In chapter 3, the one-to-four power splitter and four-to-one power combiner have been designed. Both of two circuits are operated in 60-GHz band, and implemented by using TSMC 65-nm CMOS process. The circuits consisted of Wilkinson power splitter/combiner and buffer amplifier. The thin-film microstrip line is used to match element for reducing effect of lossy substrate. The measured insertion gain of one-to-four power splitter at output port 1 and port 2 are -0.9 to 3 dB and 2.9 to 4.9 dB, respectively. The operation frequency is from 57 GHz to 65 GHz. The minimum measured isolation is 16.7 dB and the minimum measured OP1dB is -3.67 dBm. The measured insertion gains of four-to-one power combiner at input port 1 and port 2 are 4.9 to 11.2 dB and 4.7 to 11.1 dB, respectively. The operation frequency is from 57 GHz to 65 GHz. The minimum measured isolation is 19.3 dB and minimum measured OP1dB is -4.83 dBm. The reason of inducing differences between measurement and simulation is discussed in this chapter. Both of two circuits are re-designed and re-simulated. In chapter 4, the one-to-four active power splitter has been designed. The proposed circuit is operated in 60-GHz band, and implemented by using TSMC 90-nm CMOS process. The current is used to split power in the design. The proposed circuit has advantages of wideband frequency response and small chip size. The measured two way insertion gains are balanced and all above 0 dB under VDD is 2 V. The measured OP1dB is near 0 dBm. To the author’s knowledge, the circuit structure is the first demonstration of 60-GHz four-way active power splitter in a standard CMOS technology. In chapter 5, the brief conclusion of the thesis is given.

並列關鍵字

Phased-array ； CMOS ； passive power splitter and combiner ； active power splitter ； 60-GHz application

參考文獻

[2] Mohammad Fakharzadeh, Mohammad-Reza Nezhad-Ahmadi, Behzad Biglarbegian, Javad Ahmadi-Shokouh, and Saﬁeddin Safavi-Naeini, “CMOS phased array transceiver technology for 60 GHz wireless applications,” IEEE Trans. Antennas Propag., vol. 56, no. 10, pp. 1093- 1104, April 2010.

[3] Kwang-Jin Koh, and Gabriel M. Rebeiz, “Silicon RFICs for phased arrays,” IEEE Microwave Magazine, vol. 58, no. 4, pp. 96 – 103, May 2009.

[4] Kuba Raczkowski, Walter De Raedt, Bart Nauwelaers, and Piet Wambacq, “A wideband beamformer for a phased-array 60GHz receiver in 40nm digital CMOS,” in IEEE Int. Solid-State Circuit Conf. Dig., Feb. 2010, pp. 40 – 41.

[5] Wei L. Chan, John R. Long, Marco Spirito, and John J. Pekarik, “A 60GHz-band 2×2 phased-array transmitter in 65nm CMOS,” in IEEE Int. Solid-State Circuit Conf. Dig., Feb. 2010, pp. 42 – 43.

[6] Emanuel Cohen, Claudio Jakobson, Shmuel Ravid, and Dan Ritter, “A bidirectional TX/RX four element phased-array at 60GHz with RF-IF conversion block in 90nm CMOS process,” in IEEE RFIC Symp. Dig., Jun. 2009, pp. 207 – 210.

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應用於60 GHz頻段功率分配器與合成器之研製

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