由於無線通訊對資料的傳輸速度要求越來越高,使得越來越多的研究著眼在60 GHz這個有7 GHz頻寬的免執照頻段。雖然傳統上,這個頻段多使用載子移動速度較快、崩潰電壓較高的三五族製程來進行電路設計,近年來,由於金氧半互補式(CMOS)製程的進步,CMOS元件已可以操作在毫米波頻段。然而,在這個頻段的主要挑戰來自於,一般用於連接接收機電路與天線的磅線,在這樣高的頻率下會產生非常大的損耗。不過幸運的是,如果如果晶片天線可以被製作在矽基板上且不會產生太大的損耗的話,則磅線所造成的損耗就可以被避免,所以在這本論文中,會主要針對在矽基板上整合60 GHz接收機電路和晶片天線去作研究。 本論文首先對矽基板上的60 GHz晶片天線去作研究與製作。另外,低雜訊放大器在接收機中也是一個很重要的元件,因此低雜訊放大器在60 GHz頻段會發生的問題會先在論文中被討論,並且提出新的放大器架構去解決這些問題。接著,一個包括晶片天線、低雜訊放大器、混波器與震盪器的接收機電路也會被實作及量測。最後並提出一種極適合用來製作微小化電路的傳輸線架構,且利用它來實現一個微小化的60 GHz低雜訊放大器。論文中所有的電路都是選用130奈米的CMOS製程來進行實作。
The need for very high data rate wireless systems has encouraged research interest on use of the 7-GHz unlicensed band around 60 GHz. Although these millimeter-wave circuit blocks are usually designed using III-V technologies because of its higher mobility and breakdown voltage, these years, they can be implemented using CMOS technologies because of the scaling of devices. However, the major challenge is at the interface between the transceiver and antenna, because bond wires usually used as the interface have high loss at 60 GHz. Fortunately, if a low-loss chip antenna on silicon can be implemented, the loss due to bond wires can be eliminated. Therefore, the integration of 60 GHz receiver and chip antenna will be investigated in the thesis. 60-GHz chip antennas on silicon are firstly studied and implemented in this research. Besides, LNA is another critical component in the receiver. Hence the issues with LNA at 60 GHz will be studied and an improved circuit topology will be introduced to resolve them. A receiver consisting of an on-chip antenna, low noise amplifier, mixer and oscillator will then be fabricated. Finally, a new transmission line structure will also be proposed. It is especially suitable to design compact silicon-based passive circuits. A 60-GHz LNA using the proposed transmission line for impedance matching is implemented. All the circuits are fabricated using 130-nm CMOS technology.