24和60-GHz互補式金氧半導體前端接收器之設計

Design of 24 and 60-GHz CMOS Receiver Front-End

陳志成(Chi-Chen Chen)

指導教授 ： 林佑昇

國立暨南國際大學/科技學院/電機工程學系/博士(2010年)

https://doi.org/10.6837/NCNU.2010.00285

摘要

本論文以24-GHz和60-GHz互補式金氧半導體接收器前端電路之設計為研究目標。此論文的前半段，我們以TSMC 0.18-μm CMOS製程技術實現了24-GHz低雜訊放大器、21-GHz接收器前端電路以及24-GHz差動I/Q輸出的接收器前端電路。在論文的後半段,我們以TSMC 0.13-μm CMOS製程技術實現了55-GHz低雜訊放大器、53.5-62-GHz寬頻低雜訊放大器、V-band單平衡式混頻器以及60-GHz接收機前端電路。
首先,從24-GHz低雜訊放大器的模擬結果可以得知，在第三級輸入端增加串接peaking inductor可以增加44%的功率增益(S21)。在第三級的RC迴授和小電阻可以讓輸出有傑出的輸出匹配。在24 GHz的量測結果顯示，功率增益和輸出返回損耗分別為10.03 dB和-35.6 dB。而且此電路的功率消耗只有3.7mW。
第二部份是21-GHz互補式金氧半導體接收機前端電路,包含低雜訊放大器和混頻器。在射頻頻率為21 GHz和中頻頻率為2.4 GHz的時候，量測的功率增益為20.3 dB，量測的雜訊指數為8.6 dB，而且此電路消耗之功率為43.2 mW。
24-GHz互補式金氧半導體直接降頻式接收機前端電路，包含一組低雜訊放大器、二組次諧波混頻器、三組微小化的正交耦合器和巴倫，以及二組中頻放大器。我們使用含有正交耦合器和巴倫的次諧波頻波器來消除LO的自我混頻。在射頻頻率為24 GHz和中頻頻率為100 MHz的時候，電路消耗之功率為62.6 mW，而且電路量測的功率增益為31.8 dB。
55-GHz低雜訊放大器的量測結果有8 dB的功率增益和5.05 dB的雜訊指數。然而，它的增益和頻寬是不夠的。為了改善上述的問題，我們設計一個由六級共源極放大器組成的53.5-62-GHz寬頻低雜訊放大器。在第二級和第四級使用電流共用技術來增加增益和頻寬，以及降低功率的消耗，為了研究低雜訊放大器的基板損耗特性，選擇性地對低雜訊放大器進行ICP (電感耦合電漿蝕刻機)晶背蝕刻後製程，由量測結果得知，ICP前和ICP後的寬頻低雜訊放大器之雜訊指數在54-63 GHz頻帶分別是5.4~8.2 dB和4.9~8 dB。
對震盪器而言，大的輸出功率和好的相位雜訊在高頻是難達成的。次諧波混頻器以及整合倍頻器的主動式混頻器只需要一半的LO頻率，因此，我們採用整合倍頻器的單平衡式主動混頻器來消除上述的問題。混頻器3-dB頻寬的量測有9.5 GHz (48.5 GHz to 58 GHz)，在53 GHz有9.5 dB的最大功率增益，而電路消耗之功率為31.5 mW。
最後，60-GHz接收機前端電路包含寬頻低雜訊放大器、混頻器、基頻放大器和威爾金森功率分配器組成，60-GHz接收機前端電路消耗之功率為50.2 mW，輸入返回損耗在52.3 GHz 到 62.3 GHz小於-10 dB。在射頻頻率為56GHz以及中頻頻率為20MHz的時候，量測到的功率增益是18 dB。3-dB頻寬有9.8 GHz (50.8 GHz to 60.6 GHz)。

關鍵字

24-GHz ； 60-GHz ； V-band ； 低雜訊放大器 ； 單平衡式混頻器 ； 次諧波混頻器 ； 接收機前端電路 ； 威爾金森功率分配器 ； 倍頻器 ； 電流共用技術

並列摘要

The aim of this thesis is to design the front-end circuits of CMOS receivers at the frequency of 24 GHz and 60 GHz, respectively. In the first half of this thesis, a low power 24-GHz low-noise amplifier (LNA), a 21-GHz CMOS receiver front-end, and a 24-GHz CMOS receiver front-end with differential I/Q output were implemented by TSMC 0.18-μm CMOS technology. In the later half of this thesis, a 55-GHz LNA, a 53.5 to 62-GHz wideband LNA, a V-band single-balanced mixer, and a 60-GHz receiver front-end were implemented by TSMC 0.13-μm CMOS technology.
First of all, the simulation result of the 24-GHz LNA shows that the power gain (S21) can be increased 44% (from 5.7 to 10.2 at 24 GHz) by adding a series peaking inductor to the input terminal in the third stage. The shunt RC feedback and a small series resistance Rd3 in the third stage were adopted to achieve excellent output impedance matching. The measured S21 and S22 are 10.03 dB and –35.6 dB at 24 GHz, respectively. In addition, the LNA only consumed 3.7 mW
Secondly, the 21-GHz CMOS receiver front-end consists of an LNA and a dual-gate mixer. At RF frequency of 24 GHz and IF frequency of 2.4 GHz, the measured conversion gain is 20.8 dB, the measured NF is and 8.6 dB. The power consumption is 43.2 mW.
A monolithic 24-GHz CMOS direct-conversion receiver is comprised of an LNA, two sub-harmonic mixers (SHMs), three miniature quadrature couplers (QCs), three miniature baluns, and two IF amplifiers. The SHMs in conjunction with the QCs and baluns are used to eliminate LO self-mixing. At RF frequency of 24 GHz and IF frequency of 100 MHz, the direct-conversion receiver dissipated 62.6 mW, the measured conversion gain is 31.8 dB.
The measured results show that the 55-GHz LNA achieves 8 dB S21 and 5.05 dB NF, gain and bandwidth of the 55-GHz LNA were not very satisfactory. A 53.5-62-GHz wideband LNA with six cascade common-source stages was designed for achieving sufficient the gain and bandwidth. The current-sharing technique in the second and the fourth stage was adopted for increasing the gain and bandwidth of the LNA. By this way, lower power consumption of wideband LNA could be achieved. To study the substrate loss affecting the performances of the LNA, the CMOS process compatible backside ICP (inductively coupled-plasma) deep trench technology was used to selectively remove the silicon underneath the LNA. Measured NF of 5.4~8.2 dB and 4.9~8 dB was achieved for the STD LNA and the ICP LNA, respectively, over the 54-63 GHz band.
The large output power and good phase noise is hard to achieve in a VCO at V-band. Both of the sub-harmonic mixers (SHMs) and active mixer with frequency doubler only need half of the LO frequency; hence we used active single-balanced mixer with frequency doubler to eliminate foregoing problems. The measured 3-dB bandwidth (W3dB) of V-band mixer is 9.5 GHz (48.5 to 58 GHz). The maximum conversion gain is 9.5 dB at 53 GHz while the consuming power is 31.5 mW.
Finally, the 60-GHz receiver front-end comprises a wideband LNA with 12.4 dB gain, a current-reused bleeding mixer, a baseband amplifier, and a 180o out-of-phase Wilkinson power divider. The receiver front-end consumed 50.2 mW and achieved input reflection coefficient at the RF port below ?10 dB for frequencies from 52.3 to 62.3 GHz. The receiver front-end achieved maximum conversion gain of 18 dB at RF of 56 GHz. The corresponding 3-dB bandwidth (W3dB) of RF is 9.8 GHz (50.8 to 60.6 GHz).

並列關鍵字

24-GHz ； 60-GHz ； V-band ； low-noise amplifier (LNA) ； single-balanced mixer ； sub-harmonic mixers (SHMs) ； receiver front-end ； Wilkinson power divider ； frequency doubler ； current-sharing technique

參考文獻

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