24GHz與60GHz CMOS功率放大器之設計

Design of 24GHz and 60GHz CMOS Power Amplifiers

黃柏諺(Bo-yang Huang)

指導教授 ： 陳文雄 教授

共同指導教授 ： 林佑昇 教授(Ph.D. Yo-Sheng Lin)

國立暨南國際大學/科技學院/電機工程學系/碩士(2013年)

https://doi.org/10.6837/NCNU.2013.00295

摘要

本論文主要是研究利用CMOS (互補式金屬氧化物半導體)製程技術來設計與具體實現操作在K頻帶與V頻帶等兩顆不同頻帶之功率放大器 (Power Amplifier) ，在設計電路的過程中我們運用了ADS (Advanced Design system) 和Sonnet等軟體來為電路進行模擬，並利用Cadence Virtuoso來進行電路的佈局，最後，在委託國家晶片中心進行晶片的下線並量測。此論文的架構可分成兩個部分:
第一部分是介紹功率放大器 (Power Amplifier) 的設計原理與特性。而第二個部分為介紹此論文的研究主軸，設計並模擬兩種不同架構之電路模型，而此兩種電路模型分別為二級的cascode架構 (運用TSMC 0.18 μm製程技術實現) 和三級common source架構 (運用TSMC 90 nm製程技術實現) 來設計之功率放大器。而在電路架構的構思之所以會使用cascode和common source等架構主要是考量到cascode架構具有消除米勒 (Miller) 效應、改善反相隔離和有較大的增益等優點，而另一個電路架構會採用common source (共源級) 架構主要是考慮到此架構有較佳的線性度以及功耗較低的特性。在量測結果與模擬結果方面，本論文中所實現的K-Band功率放大器，所得到的量測值為:增益 (S21)=20±1.67 dB、輸出飽和功率(Psat)=15.6 dBm、OP1dB=12.56 dBm、最大功率附加效率(PAE)=13.7% ，而晶片整體面積(含test pads)=0.576 x 0.969 mm2including test pads)、電路整體消耗之功率=191.1mW。而在V-Band放大器的模擬結果方面，我們得到的模擬結果為:電路的3-dB頻寬為13GHz (53~66GHz)，增益(S21)為13.45±1.64 dB (pre-simulation)和14.17±1.75 dB (post-simulation)，輸出飽和功率(Psat)為9.81dBm (pre-simulation)和9.53dBm (post-simulation)，最大功率附加效率(PAE)為16.1% (pre-simulation)和16% (post-simulation)，而電路整體消耗之功率為53.7mW (pre-simulation)和46.2 mW (post-simulation)，且含test pads之晶片面積則是0.827x0.739 mm2.

關鍵字

K頻帶 ； V頻帶 ； 疊接 ； 共源級 ； 功率放大器 ； 功率附加效益 ； 輸出飽和功率

並列摘要

The purpose of this paper is to research into design and achieve different frequency band of power amplifier which operated in K-band and V-band by CMOS (Complementary Metal-Oxide-Semiconductor) process technology. In the circuit design process, we use softwares of ADS (Advanced Design system) and Sonnet to simulate the circuit and use Cadence Virtuoso to layout circuit, finally, the fabrication and measurement of the PA (Power Amplifier) in this paper are supported by CIC. This paper can be divided into two parts：The first part will introduce the power amplifier design principles and characteristics. The second part of this paper describes the spindle of this paper, then we design and simulate the circuit model for two different architectures, and the circuit models are two stages of cascode architecture (use TSMC 0.18 μm process technology to achieve) and three stages of the common source architecture (use TSMC 90 nm process technology to achieve). So we use cascade and common source architecture to design power amplifier.
We use cascode and common source circuit architecture, it is mainly because of cascode architecture can eliminate the Miller effect and improve the inverting isolation, and another circuit architecture uses the common source (CS) architecture, it is mainly because of the CS architecture has better linearity and low power consumption characteristic. In the measurement results and simulation results, the measurement results of the K-band Power Amplifier in this paper, the results are as following: gain(S21)=20±1.67 dB, output saturated power (Psat)=15.6 dBm, OP1dB=12.56 dBm, PAE=13.7% , and chip area=0.576 x 0.969 mm2 including test pads), DC power consumption=191.1mW, and the simulation results of V-band Power amplifier in this paper, the results are as following: 3-dB bandwidth of circuit is 13 GHz (53 ~ 66GHz), the gain (S21) is 13.45 ± 1.64 dB (pre-simulation) and 14.17 ± 1.75 dB (post-simulation), the output saturated power (Psat) is 9.81 dBm (pre-simulation) and 9.53 dBm (post-simulation), the maximum power added efficiency (PAE) is 16.1 % (pre-simulation) and 16 % (post-simulation), and total power consumption is 53.7 mW (pre-simulation) and 46.2 mW (post-simulation), and the chip area is 0.827x0.739 mm2(including test pads).

並列關鍵字

K-Band ； V-Band ； cascode ； common source ； power amplifier ； power added efficiency ； output saturated power

參考文獻

[1] J.F. Chang, “Analysis and Design of Low-Power CMOS Distributed Low-Noise Amplifiers and Low-Insertion-Loss CMOS band-pass filters”. Unpublished doctoral dissertation, National Chi-Nan University, Taiwan, 2011.

[2] CIC訓練課程(C604), “Power Amplifier Design and Simulation using ADS:

Training Manual”, pp.54, July. 2010.

[3] J.W. Lai, A. Valdes-Garcia, “A 1 V 17.9 dBm 60 GHz Power amplifier in standard 65nm CMOS ”, IEEE International Solid-State Circuits Conference, pp.425, Feb. 2010.

[4] S.H. Wang, “The Design and Simulation of a 24 GHz Class-A Cascode Configured Power Amplifier”. Master dissertation, National Sun Yat-sen University, Taiwan, pp. 42-57, Jan. 2012.