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  • 學位論文

77 GHz及94 GHz CMOS壓控震盪器之設計與實現

Design and Implementation of 77 GHz and 94GHz CMOS VCO

指導教授 : 林佑昇
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摘要


本篇論文主要是使用台積電90奈米CMOS製程元件,藉以設計與實現77 GHz及94 GHz CMOS壓控震盪器。而研究主題由以下三個部分構成: 第一部分為應用於毫米波系統之77-81 GHz壓控震盪器。為了達到較高良率,利用可調式源極衰減技術降低MOS寄生電容Cgs及提高可調範圍。模擬結果顯示使用傳統無可調式源極衰減技術之可調範圍為3.37 GHz (從73.39 GHz到76.76 GHz)。而使用此技術後可調範圍為5.11 GHz (從76.54 GHz到81.65 GHz),在提升操作頻率的條件下並且進而提高額外的可調範圍為1.74GHz (從73.39 GHz到76.54 GHz),在0.8 V電壓供應下,其電流為 6.4 mA,並且在輸出功率 -7.84 dBm偏移10 MHz時量測之相位雜訊為-111.35dBc/Hz,最後在偏壓和閘源電壓端加上旁路電容使整體電路更為穩定。 第二部分延續上部電路架構,我們設計了94 GHz壓控震盪器。與其壓控震盪器不同的地方在於:第一、調整VT1使震盪頻率隨著VT1提高而增加。然而,內建的MOS可變電容在VT1增加後,電容性下降時導致Q值不佳,因此,我們提出使用MOSFET將源極和汲極以及基體短路的方式取代內建的可變電容。由模擬的結果看出,使用MOSFET三極短路的方式在相同電容值的情況下,能夠有效提高Q值。第二、使用電流鏡架構透過改善尾部電流來降低壓控震盪器之相位雜訊,此震盪器中心消耗之功率為8.33 mW,在輸出功率 -20.94 dBm偏移10 MHz時量測之相位雜訊為-101.92dBc/Hz。此結果適合應用於94 GHz氣象雷達系統。 第三部份嘗試製作一個應用於V頻段與W頻段的Push-Push壓控振盪器,利用中心抽頭電感技術達到Push-Push的效果以便實現雙頻帶的應用以及提高2倍頻率的可調範圍並且探討V頻段與W頻段所帶來的影響,而其元件皆使用台積電90奈米製程,使電路能夠操作在高頻。

並列摘要


The purpose of this thesis is to design and implement of 77 GHz and 94 GHz CMOS VCO. The thesis can be divided into three parts: In the first part, a 77-81 GHz Voltage Controlled Oscillator (VCO) is designed for MMW system application. In order to achieve the highest values, utilizing the tunable source-degeneration technique to decrease the MOS parasitic capacitor Cgs and increase the tuning range. The simulated results show that a tuning range is 3.37 GHz (from 73.39 GHz to 76.76 GHz) without using the tunable source-degeneration technique. After using this technique, a tuning range is 5.11 GHz (from 76.54 GHz to 81.65 GHz). There is enhance for operation frequency in this condition and we further enhance the tuning range of 1.74GHz (from 73.39 GHz to 76.54 GHz), a supply voltage of 0.8 V and a supply current of 6.4 mA. The circuit delivers maximum output power of -7.84 dBm and yields a phase noise -111.35 dBc/Hz at 10 MHz frequency offset, we put bypass capacitances at the “VDD” and “VGS” term to make our circuit more stable. The second part is continuous the first chip, we design the 94 GHz VCO. The differences between the first and the second VCO are described as below: first, the oscillation frequency increases with the increase of VT1, however, the built-in MOS varactor exhibits a poor quality factor while the capacitance decrease with the increase of VT1. As a result, we replace the built-in MOS varactor with the MOSFET whose source, drain and body are shortened. The simulation results show that using MOSFET with three regions shortened under the condition of close capacitance can effectively increase the quality factor. Second, improving the structure of the current mirror can reduce the phase noise of the VCO. The power consumption of the VCO core is 8.33 mW from the 1 V power supply, the circuit delivers maximum output power of -20.94 dBm and yields a phase noise of -101.92 dBc/Hz at 10 MHz frequency offset. The result of this design can be used for 94 GHz weather radar systems. In the last part, we attempt to fabricate a push-push VCO for V-Band and W-Band. Utilizing the center tapped inductor technology by push-push structure to achieves the two-band system application and double the tuning range in frequency. The influence of V-Band and W-Band is discussed in this case. We also use TSMC 90 nm devices, which are useful for our design to operator at high frequency.

參考文獻


[1] 林佑昇,邱弘緯,梁效彬 編著(2011) : RFID 晶片設計。
[2] Bodhisatwa Sadhu, Mark Ferriss, Alberto Valdes-Garcia, “A 46.4–58.1 GHz Frequency Synthesizer Featuring a 2nd Harmonic Extraction Technique that Preserves VCO Performance,” Radio Frequency Integrated Circuits Symposium, 2014 IEEE.
[3] Pen-Li You and Tzuen-Hsi Huang, “A Switched Inductor Topology Using a Switchable Artificial Grounded Metal Guard Ring for Wide-FTR MMW VCO Applications,” Electron Devices, IEEE Transactions on (Volume:60 , Issue: 2 ), 2013 IEEE
[4] Q. Wu et al., “Design of wide tuning-range mm-wave VCOs using negative capacitance,” in Proc.IEEE Compound Semicond. Integr. Circuit Symp. (CSICS),Oct. 2012.
[5] Kun-Hung Tsai and Shen-Iuan Liu, “A 43.7mW 96GHz PLL in 65nm CMOS,” Solid-State Circuits Conference - Digest of Technical Papers, 2009. IEEE Internationa, ISSCC 2009.

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