24GHz與60GHz CMOS 功率放大器之設計與實現

Design and Implementation of 24GHz and 60GHz CMOS Power Amplifiers

張璟寧(Jing-Ning Chang)

指導教授 ： 林佑昇

國立暨南國際大學/科技學院/電機工程學系/碩士(2012年)

https://doi.org/10.6837/NCNU.2012.00290

摘要

本論文以高功率附加效率之功率放大器為研究目標。我們設計與實作了兩顆應用在不同頻段的功率放大器。研究主題主要分成兩部分:
第一部分，我們利用0.18μm CMOS製程設計並實現了一顆應用在K頻帶之高功率附加效率的功率放大器。在電路架構方面，前兩級我們以基本的疊接架構來實現，可以消除米勒效應，改善反向隔離度。最後一級則是採用了Wilkinson功率分配器架構以達到輸出功率以及功率附加效率的提升。量測結果顯示此電路操作在23~26.5GHz時，增益(S21) 為22± 1.014dB，飽和輸出功率(Psat)為15.92dBm，最大功率附加效率(PAE)為14.46%，而電路整體消耗之功率為163.8mW，且不含test pads之晶片面積為0.687 mm2。依照量測結果可以得知此電路有著不錯的特性並且適合應用於K頻帶的發射機系統。
第二部分是一個以90奈米製程實現的應用在V頻帶的高功率附加效率之功率放大器。此電路架構分成三級，前兩級以基本的共源級(CS)架構來實現，主要是考慮到此架構有較佳的線性度以及功耗較低的特性。而最後一級我們則是使用功率等分(power
splitting/combining)的架構來實現，主要目的是為了要達成高輸出功率以及高功率附加效率。而與第一部分的Wilkinson功率分配器架構不同的地方是此架構可以不需要額外的電阻以減少晶片面積並且較容易完成電路級間匹配，不過在電路穩定以及對稱上則是不如Wilkinson功率分配器的架構。量測結果顯示此電路的3-dB頻寬為13GHz(52~65GHz)，增益(S21) 為11.742± 1.49dB，飽和輸出功率(Psat)為11.37dBm，最大功率附加效率(PAE)為15.81%，而電路整體消耗之功率為44.4mW，且不含test pads之晶片面積則是0.398 mm2。本電路在最大功率附加效率(PAE)以及整體消耗功率上有突出的表現，而整體的特性與歷年文獻比較亦有不錯的表現。此電路非常適合整合於V頻帶的發射機系統中。

關鍵字

功率放大器 ； 功率附加效率 ； 輸出飽和功率 ； K頻帶 ； V頻帶 ； 疊接 ； Wilkinson 功率分配器 ； 共源級 ； 功率等分 ； 發射機

並列摘要

The purpose of this thesis is to research high added efficiency (PAE) power amplifier. We design and implement two power amplifiers, which apply for different frequency bands. The thesis con be divided into two parts：
The first part is on the design and implement of a high added efficiency power amplifier for K-band applications in 0.18μm CMOS technology. In this circuit, we used the cascade-stage structure as first two stages to eliminate the Miller effect and improve the reverse isolation. In the cause of improving the output power and power added efficiency, we use the Wilkinson power divider/combiner to implement final stage. The measured results show that this circuit operating on 23~26.5GHz, the gain (S21) is 22± 1.014dB, saturation output power (Psat) is 15.92dBm, max power added efficiency (peak PAE) is 14.46%, total power consumption is 163.8mW and the chip area (excluding test pads) is 0.687mm2. These results indicate that this circuit performs well and is suitable for K-band transmitter systems.
The second part is on the design and implement of a high added efficiency power amplifier for V-band applications in 90nm CMOS process. This circuit could be divided into three stages. The first two stages are implemented with single device common-source topology, which have better linearity and lower power consumption. In order to achieve the higher output power and higher power added efficiency, the technique of power splitting/combining is used in final stage. Not like the Wilkinson power divider/combiner in the first part. This structure need not have added resistors. So the chip area could be saved and it is easy to achieve inter-stage matching. But in stability and symmetry of structure, this power splitting/combining structure is worse than Wilkinson power divider/combiner. The measured results show that 3-dB bandwidth of this power amplifier is 13GHz (52~65GHz), gain (S21) is 11.742± 1.49dB, saturation output power (Psat) is 11.37dBm, max power added efficiency (peak PAE) is 15.81%, total power consumption is 44.4mW and the chip area (excluding test pads) is 0.398mm2. This circuit performs well in power added efficiency (PAE) and total power consumption. Compared with other conference papers, this circuit still has good performance. This power amplifier is very ideal for V-band transmitter systems.

並列關鍵字

power amplifier (PA) ； power added efficiency (PAE) ； saturation output power(Psat) ； K-band ； V-band ； cascade ； Wilkinson power divider/combine ； common source (CS) ； power spitting/combining ； transmitter

參考文獻

[1] CIC訓練課程(C604), “Power Amplifier Design and Simulation using ADS:

Training Manual”, pp.54, July-2010

[2] Behzad Razavi, RF microelectronics. Prentice Hall PTR, 1998

[3] 陳科后(2004).The Design and Implementation of Power Amplifier, Low Noise Amplifier and Wideband Amplifier. Unpublished master dissertation, National Chi-Nan

University, Taiwan.