3.1-10.6GHz CMOS 超寬頻低雜訊放大器之設計及實現

Design and Implementation of 3.1-10.6GHz CMOS Ultra-Wideband Low-Noise Amplifiers

李仁豪(Jen-How Lee)

指導教授 ： 林佑昇

國立暨南國際大學/科技學院/電機工程學系/碩士(2007年)

https://doi.org/10.6837/NCNU.2007.00003

摘要

本論文以超寬頻(Ultra-wideband)低雜訊放大器和一個用於802.11a的壓控震盪器為研究目標，研究主題分成三個部分：
第一部分探討在矽基板鋪上網狀深溝槽，以屏蔽惱人的渦流損耗，進而對電感有所改善。
第二部份為應用於接收端超寬頻系統之3.1~10.6 GHz低雜訊放大器。主要設計一個利用電阻負回授技巧之低雜訊放大器，並配合Inductive peaking技術來增加主極點頻率，進而擴展3 dB頻寬。
此二級低雜訊放大器組態為疊接再串接一個共源級放大器；在此以TSMC018 CMOS完成了三組低雜訊放大器依序分別為多個電感配合電阻負回授方式、在電感下方使用網狀深溝槽屏蔽及部分接地屏蔽，最後把輸出端的電感用電阻取代。實驗結果顯示：第一組放大器，3 dB頻寬可達10.8 GHz，在頻段3.1~10.6 GHz，S21皆維持11.4±0.4 dB的增益，輸入、輸出反回損耗皆小於-8.4 dB，以及最低雜訊指數為4.12 dB，此電路消耗之功率為22.7 mW。第二組放大器在3.1~10.6 GHz頻率下，S21皆維持11.15±0.65 dB的增益，輸入反回損耗低於-9.84 dB，輸出反回損耗低於-7.89 dB，以及雜訊指數為3.14~3.59 dB，此電路消耗之功率為23.4 mW。第三組放大器在3.1~10.6 GHz頻率下有著最高增益S21為12 dB，輸入反回損耗低於-9.32 dB，輸出反回損耗低於-4.82 dB，以及雜訊指數為4.15~4.85 dB，此電路消耗之功率為29.5 mW。
第三部份藉由TSMC018 CMOS製程，來實現一個全部採用PMOS電晶體為核心架構的5.8 GHz壓控震盪器。並且分別在電感正下方用部分接地和中間接地屏蔽來改善電感的品質因素，進而改善相位雜訊。

關鍵字

低雜訊放大器 ； 超寬頻低雜訊放大器 ； 電感補償 ； 電阻負回授 ； 壓控震盪器 ； 部分接地屏蔽

並列摘要

This thesis aim is to design an ultra wideband low noise amplifier and a voltage-controlled oscillator for 802.11a applications. Study the theme be divided into three parts：
The first part is to study the improvement of inductor on silicon substrate by using trench isolation mesh to overcome the eddy current.
In the second part, 3.1 ~ 10.6 GHz low noise amplifier is designed for ultra wideband (UWB). The mainly a kind of low noise amplifier was designed by resistive feedback loops and inductive peaking technique to enhance the frequency of the dominant pole and then expand 3 dB bandwidth of the LNA.
The two stages amplifier is composed of a cascade and a common source. The three types of low noise amplifier are implemented in TSMC018 CMOS process, the first type is multiple inductors with multiple resistors negative feedback. The second type uses trench isolation mesh and partial pattern ground shield underneath inductors. The third type translates the output inductor into resistor.
The first type of the amplifier, measured results show that the 3dB bandwidth is 10.8 GHz, the power gain (S21) of 11.4±0.4 dB, input return loss (S11) and output return loss (S22) below -8.4 dB and minimum noise figure of 4.12 dB over 3.1-10.6 GHz while consuming 22.7 mW. The second type of the amplifier measured results show the power gain (S21) of 11.15±0.65 dB, input return loss (S11) below -9.84 dB, output return loss (S22) below -7.89 dB and noise figure of 3.14~3.59 dB form 3.1 to 10.6 GHz. The total power consumption is 23.4 mW. The third type of the amplifier, measured results show the maximum power gain (S21) of 12 dB. The input return loss (S11) is less than -9.32 dB, output return loss (S22) below -4.82 dB and minimum noise figure of 4.15~4.85 dB over 3.1-10.6 GHz while consuming 29.5 mW.
In the third part, we implement a 5.8GHz P-MOS only voltage-controlled
oscillator in TSMC018 CMOS process. In addition, we also adopt the partial pattern ground shield (PPGS) and center pattern ground shield (CPGS) underneath the inductor to enhance the quality factor of inductor and improve the phase noise of implemented VCO.

並列關鍵字

low noise amplifier ； ultra wideband ； inductive peaking ； resistors negative feedback ； voltage-controlled oscillator ； partial pattern ground shield

參考文獻

[1] C. P. Yue and S. S. Wong, “Physical modeling of spiral inductors on silicon,” IEEE Trans. Electron Devices, vol. 47, pp.560-568, Mar. 2000.

[2] Jin-Cai Wen and Ling Ling, “A Wide-Band Equivalent Circuit Model for CMOS On-Chip Spiral Inductor.” Solid-State and Integrated Circuit Technology, OCT. 2006, pp. 1383-1385

[3] H. B. Liang, Y. S. Lin, C. C. Chen, and J. H. Lee, “Optimization of PGS Pattern of Transformers/Inductors in Standard RF BiCMOS Technology for RFIC Applications,” Proceedings of 2006 IEEE Radio Frequency Integrated Circuits Symposium, 11-14.

[4] Hsin-Lung Tu, I.-Shan Chen, Ping-Chun Yeh, and Hwann-Kaeo Chiou, “High Performance Spiral Inductor on Deep-Trench-Mesh Silicon Snbstrate.” IEEE MICROWAVE AND WIRELESS COMPONENTS LETTERS, VOL. 16, NO. 12, DECEMBER 2006.

[5] Gray, Pual R. etc., “Analysis and design of analog integrated circuit,” fourth edition, 2001.