寬頻低雜訊放大器與濾波器於CMOS製程實現

本篇論文主要是探討寬頻低雜訊放大器結合寬頻濾波器之設計與分析。在寬頻低雜訊放大器的設計中，使用了兩級的放大器架構，以達到寬頻的特性。其中第二級放大器中使用中間級共振電路架構（Inter-Stage Resonance），達到寬頻的增益，並使用並聯尖峰(shunt-Peaking)的頻寬延伸技術來完成寬頻特性。而在寬頻濾波器設計上，使用了雙π型（Double-π）濾波器架構，以實現在頻寬中有平坦增益，而在頻寬外有快速衰減的效果。所設計的寬頻低雜訊放大器的模擬結果如下：頻寬為3 ~ 8 GHz，平均增益為16 dB，雜訊指為4.6 ~ 5.4 dB，輸入反射係數為 <12 dB，input P1dB最小值為-23.4 dBm，IIP3最小值為-11dBm，功率消耗為14.25 mW。

關鍵字

低雜訊放大器；並聯尖峰

並列摘要

This thesis discusses the design and analysis integration of an ultra wideband low-noise amplifier and a wideband filter. In order to obtain the wide-band performance, the 2nd stage amplifier structures be used in the design of the wideband low-noise amplifier. The 2nd stage amplifier used the inter-stage resonance structure to achieves the wideband gain, the shunt-peaking technique is used to extend the bandwidth. The double-π filter structure is used in the wideband filter design to achieves the gain flatness and the sharp attenuation out of the desired band. The simulation results of the amplifier are as follows:：The bandwidth is 3 ~ 8 GHz. The average gain is 16 dB. The noise figure is 4.6 ~ 5.4 dB. The input return loss is <12 dB. The input P1dB(min.) is -23.4dBm. The IIP3(min.) is -11dBm. The power consumption is 14.25 mW.

並列關鍵字

LNA ； Shunt-Peaking

參考文獻

[5] B. Razavi, Design of analog CMOS Integrated Circuits, McGraw-Hill Education, 2000

[6] Yi-Jing Lin, Shawn S. H. Hsu, Member, IEEE, Jun-De Jin, and C. Y. Chan, “A 3.1–10.6 GHz Ultra-Wideband CMOS Low Noise Amplifier With Current-Reused Technique” in IEEE MWCL, March 2007

[7] A. Bevilacqua and A. M. Niknejad, “An ultra-wideband CMOS LNA for 3.1 to 10.6 GHz wireless receiver,” in IEEE ISSCC Tech. Dig., 2004, pp. 382–383.

[8] D. K. Shaeffer and T. H. Lee, “A 1.5-V, 1.5-GHz CMOS Low Noise Amplifier”, IEEE Journal of Solid-State Circuits, vol. 32, NO. 5, p745~p759, May 1997

[9] Friis, H.T. ”Noise Figures of Radio Receiver”, Proc. of the IRE, July, 1944, pp. 419-422

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寬頻低雜訊放大器與濾波器於CMOS製程實現

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