應用於射頻接收機之CMOS低雜訊放大器及前端電路之設計與實現

Application in RF Receivers of CMOS Low Noise Amplifiers and Front-end Circuits Design and Implementation

鄭翔駿(Hsiung-Chen Chung)

指導教授 ： 林佑昇

國立暨南國際大學/科技學院/電機工程學系/碩士(2009年)

https://doi.org/10.6837/NCNU.2009.00064

摘要

本論文主要以CMOS製程去實現射頻接收機前端電路，研究主題大致上可分成四個部分：
第一部份為3.1-10.6-GHz頻段，使用兩級共源級實現低雜訊放大器，藉由提供第一級偏壓以及電阻回授來達到降低雜訊，使用peaking技巧可增加頻寬，且以台積電0.18 um 1P6M的互補式金氧半製程實現。
第二部份為K頻段窄頻低雜訊放大器之比較，包含標準型、電感-電容之回授型、和電流再利用型，去比較三種電路設計技巧和其效能差異。最後以台積電0.18 um 1P6M互補式金氧半製程實現。
第三部份為呈現20-27-GHz寬頻低雜訊放大器，我們使用第二部份標準型電路作改良，再使用peaking技巧去增加頻寬，來達到所需求之效能，其分別採用台積電0.18 um 1P6M和0.13 um 1P8M互補式金氧半製程實現。
第四部份為接收機之前端電路，包含低雜訊放大器和混頻器組成，低雜訊放大器承接第三部份電路去整合整體系統，混頻器第一級使用穩流和第二級使用疊接方式，使其有低電流消耗和較大增益，其分別採用台積電0.18 um 1P6M互補式金氧半製程實現。

關鍵字

低雜訊放大器 ； 前端電路 ； 電流再利用 ； 混頻器

並列摘要

The thesis mainly uses CMOS process technology to implement the RF receiver front-end circuit, the thesis are composed of four sections:
The first part is LNA working at frequency 3.1-10.6-GHz, incorporated with two common sources topology to implement this LNA. The bias at first stage and resistor feedback is used to achieve to lower noise figure. The technique can increased bandwidth using peaking technology, which is implemented in TSMC 0.18um one-poly-six-metal (1P6M) CMOS process.
The second part is the K-band LNA comparison including the standard type, the inductor-capacitor feedback type, and the current reuse type. We compare three types of design and difference of performance, implemented in TSMC 0.18um one-poly-six-metal (1P6M) CMOS process.
The third part is at frequency of 20-27-GHz broadband LNA, the standard type is improved to second part. Peaking technology is used to increase bandwidth, implemented in TSMC 0.18um one-poly-six-metal (1P6M) and TSMC 0.13um one-poly-eight-metal (1P8M) CMOS process.
The fourth part is the receiver of front-end. The circuit included LNA and Mixer. Following by the third part of LNA, combined the overall system. The Mixer is used the stable current method in the first stage and cascode method in the second stage, which can achieve lower current consumption and larger gain, implemented in TSMC 0.18um one-poly-six-metal (1P6M) CMOS process.

並列關鍵字

LNA ； Front-end ； Current Reuse ； Mixer

參考文獻

[1]Kyung-Wan Yu”, Yin-Lung Lu”, Daquan Huang’’, Da-Chiang Chang”, Victor Liang”, and M. Frank Chang” “A 26 GHz Low-Noise Amplifier in 0.18um CMOS Technology” IEEE, 2003.

[2]FCC, First Report and Order 02-48, February 2002.

[3]Freescale Semiconductor “Ultra-Wideband Opportunities Under the New FCC Waiver,” Rev1 March / 2005.

[4]B. Razavi, “RF Microelectronics,” Prentice-Hall, Inc., 1998.

[5]A. Bevilacqua, and A. M. Niknejad, "An Ultrawideband CMOS Low-Noise Amplifier for 3.1-10.6-GHz Wireless Receivers," IEEE J. Solid-State Circuits, vol. 39, no. 12, pp. 2259-2268, Dec. 2004.