CMOS低雜訊放大器與收發開關之研製

Implementation of CMOS Low Noise Amplifiers and T/R Switch

李子康(Zi-Kang Li)

指導教授 ： 王紳

國立臺北科技大學/電資學院/電腦與通訊研究所/碩士(2012年)

https://doi.org/10.6841/NTUT.2012.00678

摘要

本篇論文的第一個部份描述一個寬頻單刀雙擲開關的設計與量測。電路設計由CMOS製程來實現低成本與高度整合的優勢。這個單刀雙擲開關的頻寬為6~30 GHz
，中心頻率18 GHz，插入損耗(IL)小於3 dB，與大於32 dB的隔絕度，線性度(P1dB)為22 dBm ±1dBm。於台積電0.18-μm 1P6M CMOS製程實現所設計的電路。晶片面積為0.476 mm2。
本篇論文的第二部份描述應用在X頻帶系統中的低雜訊放大器之分析與設計。X頻帶的低雜訊放大器需具備有寬頻、低功率、增益平坦的特性，為了達到寬頻與低雜訊的目標，利用多級的概念來設計，並且選擇採用共源級做為第一級放大，與兩個共源級作為最後一級。這個寬頻低雜訊放大器的頻寬為8 ~ 12 GHz，增益為14 dB ±1dB，雜訊指數最低 2.8 dBm，消耗功率為9.78 mW。最後的硬體實現是使用台積電0.18-μm 1P6M CMOS 製程；其晶片大小為 0.476mm2。

關鍵字

單刀雙擲開關 ； X-Band ； 低雜訊放大器 ； 變壓器

並列摘要

The first part of the thesis describes design and measurement of a wideband single-pole double-throw (SPDT) switch. The circuit design based on CMOS technology achieves the advantages of low cost and high integration capability. The bandwidth of the SPDT switch ranges from 6 to 30 GHz centered at 18 GHz. The insertion loss is less than 2 dB, and the isolation is better than 32 dB. The P1dB is 22 dBm ± 1 dBm. The implementation of the designed circuit is based on TSMC 0.18-μm CMOS 1P6M process. The overall chip size is 0.476 mm2.
The second part of the thesis describes the design and analysis of a low-noise amplifier for X-Band system. The features of the LNAs are wide bandwidth, low power consumption and flatness of gain. In order to get wide bandwidth and low noise, we utilize the concept of multi-stages to design this circuit. The first stage is a common source topology and two common source amplifiers in the second stage. The bandwidth of the LNA ranges from 8 GHz to 12 GHz. The gain is 14 dB ± 1 dB. The minimum noise figure is 2.8 dB and the power consumption is 9.78 mW. Finally, the circuit is implemented with TSMC 0.18-μm CMOS 1P6M process with a chip size of 0.464 mm2.

並列關鍵字

SPDT ； SwitchX-band ； Low-Noise Amplifiers (LNA) ； Transformer

參考文獻

[1] B. Razavi, RF Microelectronics, McGrawHill, Inc. 2003.

[2] F. J. Huang and K. K. O, “A 0.5 μm CMOS T/R switch for 900 MHz wireless applications,” IEEE J. Solid-State Circuits, vol. 36, pp. 486–492, Mar. 2001.

[3] K. Yamamaoto, T. Heima, A. Furukawa, M. Ono, Y. Hashizume and H. Komurasaki, “ A 2.4 GHz-band 1.8 V operation single-chip Si-CMOS T/R-MMIC front-end with a low insertion loss switch,” IEEE J. Solid-State Circuits, vol. 36, pp. 1186–1197, Aug 2001.

[4] T. Ohnakado, A. Furukawa, M. Ono, E. Taniguchi, S. Yamakawa, K. Nishikawa, T. Murakami, Y. Hashizume, K. Sugahara, and T. Oomori, “A 1.4 dB insertion-loss, 5 GHz transmit/receive switch utilizing novel Depletionlayer- Extended Transistors (DETs) in 0.18 um CMOS process,” in VLSI Tech. Dig., Mar. 2002, pp. 162–163.

[5] Z. Li, H. Yoon, F. J. Huang, and K. O, “ A 5.8-GHz CMOS T/R switches with high and low substrate resistances in a 0.18-μm CMOS process,” IEEE Microwave Wireless Compon. Lett, vol. 13, pp. 1–3, Jan. 2003.