5GHz CMOS超低功率射頻前端電路之設計與實現

Design and Implementation of 5-GHz CMOS Ultra-Low-Power Receiver Frontends

鍾國聖(Kuo-Sheng Chung)

指導教授 ： 呂良鴻

國立臺灣大學/電機資訊學院/電子工程學研究所/碩士(2005年)

https://doi.org/10.6342/NTU.2005.10215

摘要

由於近年來CMOS 在高頻特性下之進展，使其成為實現低價無線通訊系統的熱
門製程。除了傳統射頻系統之外，CMOS 也應用於低功率、低電壓之積體化電路，例
如：射頻識別(RFID)與無線感測網路(wireless sensor networks)等。然而，因為CMOS
製程固有地低轉導(transconductance)特性與起始電壓(threshold voltage)的需求，使其
難以在低電壓與低功率下應用。在本論文中，我們利用標準0.18-μm CMOS 製程實現
一降頻混波器、電壓控制振盪器與一射頻前端接收器，由這些電路驗證了CMOS 射
頻前端電路在低電壓與低功率操作下之可能性。
結合堆疊互補式(complementary)電晶體與電流分流(current bleeding)電阻兩種技
術，此一新穎的混波器可在低電源供應之下維持一合理的轉換增益(conversion gain)。
在0.6V 的電源供應與792μW 的功率消耗之下，5.2-GHz 的混波器可達到3dB 轉換增
益與-8dBm 輸入三階交叉點(IIP3)。至於電壓控制振盪器方面，藉由省略LC 振盪器的
電流源來達成超低電壓的目標。在0.6V 的供應電壓與696μW 的功率損耗之下，
5.8-GHz 的電壓控振震盪器可達到調變範圍8.9%與相位雜訊-97dBc/Hz@1MHz。最
後，組合先前的混波器、電壓控制震盪器與一單級低雜訊放大器來實現一5GHz 射頻
前端接收器。由模擬結果可知，射頻前端接收器可達到轉換增益15dB 與輸入三階交
叉點-19dBm。在0.6V 的低電壓之下，整個射頻接收器只需2.3mW 功率損耗。

關鍵字

低電壓 ； 低功率 ； 射頻前端接收器

並列摘要

With recent advances in the high-frequency characteristics, CMOS has become very
attractive process for the implementation of low-cost wireless communication systems. In
addition to conventional RF systems, low-power and low-voltage applications, such as
RFID and wireless sensor networks, have motivated the development of fully integrated
transceivers using CMOS process. However, the inherently low transconductance and the
required threshold voltage for CMOS process make it extremely difficult to operate
reduced supply voltage and power dissipation. In this thesis, a down-conversion mixer, a
voltage-controlled oscillator (VCO) and a receiver frontend fabricated in 0.18-μm CMOS
are presented to demonstrate the potential of CMOS frontend circuits for low-power and
low-voltage operation.
A novel mixer with stacked complementary transistors and a current bleeding resistor is
proposed for low-voltage application while maintaining reasonable conversion gain. The
5.2-GHz mixer exhibits a conversion gain of 3dB and an IIP3 of -8dBm with a power
dissipation of 792 μW from a 0.6-V supply voltage. As for the proposed VCO topology, the
tail current source of a LC-tank VCO has been eliminated to support ultra-low voltage
operation. 5.8-GHz VCO achieves a tuning range of 8.9% and phase noise of -97dBc/Hz
@ 1MHz. The VCO core consumes 696-μW dc power from a 0.6-V supply voltage. Finally,
by combining the fabricated mixer, VCO with a single stage LNA, the receiver frontend is
designed for the 5-GHz frequency band. Based on the simulation results, the receiver
frontend demonstrates a conversion gain of 15dB and IIP3 of -19dBm. The complete
receiver is operated at a reduced supply voltage of 0.6 V with a power dissipation of
2.3mW.

並列關鍵字

low voltage ； low power ； receiver frontend

參考文獻

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