1GHz CMOS 鎖相迴路之頻率合成器之晶片設計與研製

Design and Chip Implementation of a 1GHz CMOS Phase Locked Loop-based Frequency Synthesizer

楊文毓(Wen-Yu Yang)

指導教授 ： 吳紹懋 ； 劉榮宜

元智大學/工程學院/電機與資訊工程研究所/碩士(1997年)

摘要

本篇論文所要介紹的是一種可工作在1GHz的CMOS鎖相迴路頻率合成器
(1GHz CMOS PLL-based Frequency Synthesizer)之設計。它包含電壓控
制振盪器(Voltage Controlled Oscillator)、相位—頻率偵測器(Phase—
Frequency Detector)、電壓幫浦(Charge Pump)、迴路濾波器(Loop
Filter)、前置除頻器(Precaler Divider)及多係數除頻器
(Multi-Modulus Divider)。

電壓控制振盪器由控制電壓來調整振盪頻率，輸出頻率從900MHz到
1.3GHz。相位—頻率偵測器比較輸入參考信號與除頻後的振盪器輸出的相位及頻
率，輸出充電UP與放電DW的數位信號。電荷幫浦將相位—頻率偵測器的數
位輸出訊號轉成電壓控制振盪器所能接受的類比訊號。迴路濾波器濾除高
頻的雜訊。前置除頻器將振盪器的輸出處理到多係數除頻器所能接受的範
圍，多係數除頻器從8到18，共有三個除數。

這個頻率合成器是用UMC 0.5 um 2P2M CMOS製程，此晶片面積含pad
為1.8 x 1.8 mm2，輸出在1.3GHz時，功率消耗為114mW。

關鍵字

相位-頻率偵測器 ； 電壓控制振盪器 ； 電荷幫浦 ； 迴路濾波器 ； 除頻器 ； 多係數除頻器

並列摘要

A 1GHz CMOS Phase Locked Loop-based Frequency Synthesizer is
presented. The synthesizer is implemented using a voltage
controlled oscillator, phase—frequency detector, charge pump,
loop filter, precaler divider and multi-modulus divider.

The voltage controlled oscillator adjusts its frequency
by controlling voltage from the charge pump. The range of the
frequency is from 900 MHz to 1.3 GHz. The phase—frequency
detector compare the reference signal*s phase and frequency
with the feedback signal. It produces two digital signal UP
and DW. The charge pump translates the digital signal of the
phase—frequency detector to the analog signal that is accepted by the voltage controlled oscillator. The loop filter can eliminate the high frequency*s noise. The multi-modulus divider is composed of three divisor.

The chip is implemented in UMC 0.5um 2P2M CMOS process
technology, and the chip area is 1.8mm x 1.8mm. The chip power
dissipation is 114mW when the input frequency is 1.3GHz.

並列關鍵字

Phase-Frequency Detector ； Voltage Controlled Oscillator ； Charge pump ； Loop Filter ； Divider ； Multi-Modulus Divider

參考文獻

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[CWC92] C. S. Chang, H. P. Wan and C. Y. Cheng, Phase-

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