使用CMOS製作之低功耗毫米波無線通訊晶片與基板天線積體化設計

A Low-Cost and Low-Power Integrated Millimeter-Wave Transceiver in CMOS with On-Board Antenna Assembly

陳彥佐(Yen-Tso Chen)

指導教授 ： 李致毅

國立臺灣大學/電機資訊學院/電子工程學研究所/碩士(2009年)

https://doi.org/10.6342/NTU.2009.01567

摘要

本論文研究設計於60GHz頻段操作之積體電路及天線，其主要應用於超高速無線傳輸。受惠於製程技術的進步，互補式金氧半導體(CMOS)元件的截止頻率已超過100GHz，並因其容易與數位電路系統積體化的緣故，使得在CMOS晶片上實現的毫米波電路系統成為一個相當有吸引力的方式。
　　本論文將簡介設計60GHz無線收發系統的考量，此外也將討論毫米波電路在晶片及封裝上碰到的困難。接著會介紹一個完全整合之60GHz收發系統，包含整合於封裝之天線；此設計使用開關鍵移調變以及低成本的天線技術，達成一個低功耗與每秒數十億位元傳輸速率的無線通訊。晶片結合天線包含折疊偶極天線以及貼片陣列天線，將做完整的測試。此晶片使用90奈米CMOS製程製作，發射機和接收機分別消耗183與103毫瓦，並使用0.43和0.68平方毫米的面積。測試在輸入長度為2^31 − 1之偽隨機碼下達到位元錯誤率小於10^−12的情況，使用折疊偶極天線在6公分的距離達到每秒15億位元的傳輸率；使用4乘3貼片陣列天線在61公分的距離達到每秒10億位元的傳輸率。此外本論文也設計了適用於覆晶封裝連結的天線，使得整個系統效能更為穩定。

關鍵字

60-GHz ； 無線收發機 ； 開關鍵移調變 ； 微帶線平板天線 ； 封裝整合天線

並列摘要

This thesis focuses on design of 60-GHz integrated circuits and antennas, which must be used for high-speed wireless transmission. Although such high frequency circuits only implemented in III-V compound semiconductor in the past, nowadays, gaining the advantage of Moore's law sustained, CMOS transistors with cut-off frequencies above 100 GHz turn out to be the best candidate for mm-Wave integrated circuits, for its familiar with digital circuits and integrated systems.
　　Design considerations for 60-GHz wireless transmission would be discussed first. Describe many challenges in design of mm-Wave circuits in silicon and interface. And then we would present a fully-integrated 60-GHz transceiver system with on-board antenna assembly. Incorporating on-off keying (OOK) modulation and low-cost antenna design, this prototype provides a low-power solution for several Gb/s wireless communications. The enhanced OOK modulator/demodulator obviates baseband and interface circuitry, revealing a compact solution. Two antenna structures, folded dipole and patch array, are employed to fully examine the performance. Connecting to chip with bond wires, we use some techniques to alleviate the impedance issues. This design is fabricated in digital 90-nm CMOS technology; the transmitter and the receiver consume 183 and 103 mW and occupy 0.43 and 0.68 mm^2, respectively. With folded dipole antenna, the transceiver demonstrates error-free operation (BER < 10−12) for 2^31 − 1 PRBS of 1.5 Gb/s over a distance of 6 cm. With 4 × 3 patch antenna arrays, the transceiver achieves error-free operation (BER < 10^−12) for 2^31 − 1 PRBS of 1 Gb/s over a distance of 61 cm. Finally, we also design the antenna on board suitable for flip-chip interconnections, which is convinced of more compact solution.

並列關鍵字

60-GHz ； Wireless transceiver ； On-off keying (OOK) ； Microstrip antenna ； Antenna in package (AiP)

參考文獻

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