低電壓低功率之CMOS射頻接收器前端電路

Low-Voltage Low-Power CMOS Radio Frequency Receiver Front-end Circuits

王日新(Jih-Hsin Wang)

指導教授 ： 呂良鴻

國立臺灣大學/電機資訊學院/電子工程學研究所/碩士(2008年)

https://doi.org/10.6342/NTU.2008.02675

摘要

本篇論文介紹低電壓低功率射頻前端接收器之設計問題與實作。在此論文中，不同的電路技巧與架構被提出與實現以降低功率消耗並解決供應電壓不足的問題。本論文共分為六個章節，首先第一章大致介紹論文組織與架構，第二章則回顧與低電壓低功率射頻前端接收器有關的背景知識。
第三章提出一個適用於低電壓之射頻接收/發射切換開關。利用非對稱之電感-電容共振腔架構，除了解決在低供應電壓下電晶體開關特性不佳之問題，更可有效達成在接收端時的低輸入損耗，與發射端之高線性度。此電路以0.18-um標準互補式金氧半導體製程實現，同時量測結果也會於本章討論並呈現。
第四章則分析低電壓之低雜訊放大器之設計問題與架構。以折疊-串疊架構為主軸，本章提出在極低功率(約1毫瓦)下，最大化電路效能之可能。另外以折疊-串疊加上一增益加強迴路以達到高增益之架構亦在此章被討論。兩種低雜訊放大器之架構均以0.18-um標準互補式金氧半導體製程實作並且加以量測。
第五章包含一個低中頻多相位濾波器之設計與實作結果。此設計採用主動式電路以降低多級濾波器串聯時，後級對前級之負載效應所造成之訊號損耗。與被動式電阻-電容多相位濾波器比較，本章所提出之架構可大幅降低達到相同信號增益下之功率消耗。
最後，結論在第六章提出並總結。

關鍵字

低電壓 ； 低功率 ； 射頻 ； 前端接收器

並列摘要

This thesis introduces the design issues and implementation of low-voltage low-power radio frequency receiver front-end circuits. To operate in heavily reduced supply voltage, different architectures and design techniques have been proposed. The thesis is organized by six chapters. The first chapter illustrates the current technology trend as an introduction. In chapter 2, the background knowledge for low-voltage low-power design is overviewed.
In chapter 3, a low-voltage radio frequency transmit/receive switch is proposed. Using inductor/capacitor resonators, this architecture successfully resolves the limitation of poor on/off characteristics of transistor due to low supply voltage. Furthermore, the switch exhibits a low insertion loss in the receive path, as well as a high power handling capability in transmit path. The circuit is implemented using a standard 0.18-um CMOS process. The experimental results are also included in this chapter.
In chapter 4, design issues and architectures of low-noise amplifier (LNA) are discussed and analyzed. Based on folded cascode architecture, methods to maximizing LNA characteristics with very low power dissipation (~1mW) are proposed. In addition, a folded cascode LNA adding a gain-enhancement loop is also realized in this chapter. Both circuits are implemented with a standard 0.18-um CMOS process and the measurement results are presented in this chapter.
In chapter 5, a low-intermediate frequency polyphase filter incorporating an active structure is implemented to decrease the signal loss due to the loading effect while cascading multistages. Compared with a traditional passive R-C polyphase filter, this low-voltage active polyphase filter using a 0.18-um CMOS process exhibits much lower power dissipation while achieving the same signal gain level.
Finally, conclusions are discussed in Chapter 6.

並列關鍵字

low voltage ； low power ； radio-frequency ； receiver front-end

參考文獻

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