應用於 5G 通訊之 28 GHz CMOS 功率放大器設計與實現

Design and Implementation of 28 GHz CMOS Power Amplifiers for 5G Communications

陳彥志(Yan-Jhih Chen)

指導教授 ： 翁偉中

共同指導教授 ： 林佑昇(Yo-Sheng Lin)

國立暨南國際大學/科技學院/電機工程學系/碩士(2020年)

https://doi.org/10.6837/ncnu202000043

摘要

本論文探討應用於 5G 通訊之功率放大器設計，利用台灣半導體研究中心所提供的 TSMC CMOS 90 nm 製程技術，在 Ka 頻段以功率組合技術設計功率放大器，內容包含電路設計、模擬分析、晶片量測、結果討論。論文整體主軸可分為三大部分：
第一個部分是以 90 奈米製程設計及實現了一個應用在 Ka 頻段的功率放大器，採用疊接級放大器來實現高增益和共源級放大器來實現高輸出功率，另外，傳統的兩路威爾金森功率組合器，可以用本論文提出的兩圈螺旋形功率組合器取代，其優勢為降低損耗及尺寸，其量測到之功率增益為 8.56 dB 、輸出功率1-dB 增益壓縮點為 2.33 dBm 、輸出三階交越點為 3.3 dBm 、輸出飽和功率為 3.66 dBm 、功率附加效率為 4.35 %、功耗為 143.112 mW、晶片面積為 0.954 × 0.999 mm^2 。
第二個部分是以 90 奈米製程設計及實現了一個應用在 Ka 頻段的功率放大器，採用兩級疊接級放大器來改善隔離度及增益，另外，傳統的兩路威爾金森功率組合器，可以用本論文提出的三圈螺旋形功率組合器取代，其優勢為降低損耗及尺寸，其量測到之功率增益為 9.93 dB 、輸出功率 1-dB 增益壓縮點為 10.59 dBm、輸出三階交越點為 12.069 dBm、輸出飽和功率為 10.61 dBm、功率附加效率為 4.46 %、功耗為 282.96 mW、晶片面積為 1.000 × 1.000 mm^2 。
第三個部分是以 90 奈米製程設計及實現了一個應用在 Ka 頻段的功率放大器，採用疊接級放大器來實現高增益和共源級放大器來實現高輸出功率，另外，傳統的兩路威爾金森功率組合器，可以用本論文提出的微小化三圈螺旋形功率組合器取代，其優勢為降低損耗及尺寸，其模擬到之功率增益為 24.012 dB 、輸出功率 1-dB 增益壓縮點為 12.015 dBm、輸出三階交越點為 21.255 dBm、輸出飽和功率為 16.232 dBm、功率附加效率為 26.049 %、功耗為 108.72 mW、晶片面積為 1.000 × 999.695 mm^2 。

關鍵字

5G 通訊 ； Ka 頻段 ； 互補式金氧半導體 ； 90 奈米 ； 功率放大器 ； 疊接級放大器 ； 共源級放大器 ； 功率組合技術 ； 功率組合器

並列摘要

This thesis presents the design of power amplifiers used in 5G communications, using TSMC CMOS 90 nm process technology provided by Taiwan Semiconductor Research Center (TSRI). The power amplifiers that using power combining techniques are manufactured for Ka-band. The content includes the circuit design, simulation analysis, chip measurement results, and a short discussion. This thesis consists of three main parts:
The first part is the design and implementation of a power amplifier for Ka-band applications in 90 nm CMOS technology, using the cascode amplifiers to achieve high gain and the common-source amplifiers to achieve high output power, the traditional 2-way Wilkinson power combiner can be replaced with the two-turn spiral shaped power combiner proposed in this thesis. Its advantages are reduced loss and size. The measured power gain (GP) is 8.56 dB, the output power of 1-dB gain compression point (OP1dB) is 2.33 dBm, the output third order intercept point (OIP3) is 3.3 dBm, the saturated output power (Psat) is 3.66 dBm, the power added efficiency (PAE) is 4.35 %, the power consumption is 143.112 mW, and the chip size is 0.954 × 0.999 mm^2.
The second part is the design and implementation of a power amplifier for Ka-band applications in 90 nm CMOS technology, using two stage cascode amplifiers to improve isolation and gain, the traditional 2-way Wilkinson power combiner can be replaced with the three-turn spiral shaped power combiner proposed in this thesis. Its advantages are reduced loss and size. The measured power gain (GP) is 9.93 dB, the output power of 1-dB gain compression point (OP1dB) is 10.59 dBm, the output third order intercept point (OIP3) is 12.069 dBm, the saturated output power (Psat) is 10.61 dBm, the power added efficiency (PAE) is 4.46 %, the power consumption is 282.96 mW, and the chip size is 1.000 × 1.000 mm^2.
The third part is the design and implementation of a power amplifier for Ka-band applications in 90 nm CMOS technology, using the cascode amplifiers to achieve high gain and the common-source amplifiers to achieve high output power, the traditional 2-way Wilkinson power combiner can be replaced with the miniature three-turn spiral shaped power combiner proposed in this thesis. Its advantages are reduced loss and size. The simulated power gain (GP) is 24.012 dB, the output power of 1-dB gain compression point (OP1dB) is 12.015 dBm, the output third order intercept point (OIP3) is 21.255 dBm, the saturated output power (Psat) is 16.232 dBm, the power added efficiency (PAE) is 26.049 %, the power consumption is 108.72 mW, and the chip size is 1.000 × 999.695 mm^2.

並列關鍵字

5G Communication ； Ka-band ； CMOS ； 90 nm ； Power amplifier (PA) ； Cascode amplifier ； Common-Source (CS) amplifier ； Power combining technique ； Power combiner

參考文獻

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