應用於毫米波CMOS之功率放大器設計與實現

Design and Implementation of Millimeter-Wave CMOS Power Amplifier

曾暐翔(Wei-Xiang Tseng)

指導教授 ： 林佑昇

國立暨南國際大學/科技學院/電機工程學系/碩士(2018年)

摘要

本論文主要是研究利用CMOS (互補式金屬氧化物半導體)製程技術來設計與具體實現操作在W頻帶之功率放大器 (Power Amplifier) ，在設計電路的過程中我們運用了ADS (Advanced Design system) 和Sonnet等軟體來為電路進行模擬，並利用Cadence Virtuoso來進行電路的佈局，最後，在委託國家晶片中心進行晶片的下線並量測。此論文的研究主軸可分成三部分：

第一部分是以一個以90奈米製程實現的應用在W頻帶的94GHz之高功率附加效率之功率放大器。在電路架構方面，以四級的共源級(CS)架構來實現，主要是考慮到此架構有較佳的線性度以及功耗較低的特性。第三級採用Y型功率分配器架構結合兩路輸出功率，第四級採用Dual-Y型功率分配器架構結合四路輸出功率，達到輸出功率以及功率附加效率的提升，量測結果顯示此電路的增益(S21) 為12±1.1dBm，飽和輸出功率(Psat)為5dBm，最大功率附加效率(PAE)為0.7%，而電路整體消耗之功率為280mW，且含test pads之晶片面積則是0.996*0.988 mm2。本電路在最大功率附加效率(PAE)以及飽和輸出功率(Psat)有不錯的表現。
第二部分是以一個以90奈米製程實現的應用在W頻帶的94GHz之功率放大器。在電路架構方面，提出三級CMOS PA，為了改善提出的PA的增益並保持CS的良好的PAE性能和穩定度，第一級採用共源級配置的正回授來確保無條件穩定。為了提高輸出功率（Pout），雙向CS增益級採用Y型分配器和合成器，和兩個四通CS採用雙Y型分配器和合成器應用於PA的最後兩個階段，電路的增益(S21) 為15.6±1.1dBm，飽和輸出功率(Psat)為14dBm，最大功率附加效率(PAE)為7.7% ，電路的功率消耗改善降低也保持著有相當不錯的增益，相對整個電路的線性度也有所提升，在Gain、Psat、OP1dB與PAE都有極佳的表現。
最後一部分設計在94GHz毫米波頻率的90奈米製程之功率放大器，晶體管的功率增益顯著降低，隨著頻率的增加。所以多級共源（CS）放大器拓撲結構中常用的最近先進的CMOS功率放大器提高增益波段。用全新設計4-way Wilkinson divider將所有的輸入和輸出匹配到50歐姆，此設計可以減少面積消耗。使用Sonnet設計微帶線和經過優化，在94GHz達到低損耗， PA unit部分使用CS放大器堆疊成三級作為放大功能，為了提高輸出功率（Pout）和PAE，在PA unit輸出端使用雙向CS增益級採用Y型分配器和合成器，不但可以減少面積，並透過 load-pull simulation 的最佳負載點 (for Pout & PAE)來達到最佳的輸出功率和PAE。
本論文，研究之電路具有高增益、高輸出飽和功率和高功率增加效益，且輸入和輸出皆有匹配 , 可應用於77~81 GHz 汽車雷達和94 GH顯像雷達系統。

關鍵字

功率放大器 ； 功率附加效率 ； 輸出飽和功率 ； W頻帶 ； 疊接 ； Y型功率分配器/結合器 ； Dual-Y型功率分配器/結合器 ； 平衡-不平衡轉換器 ； 共源級

並列摘要

The purpose of this paper is to research into design and W-band of power amplifier which operated in W-band by CMOS(Complementary Metal-Oxide-Semiconductor) process technology. In the circuit design process, we use software of ADS (Advanced Design system) and Sonnet to simulate the circuit and use Cadence Virtuoso to layout circuit, finally, the fabrication and measurement of the PA (Power Amplifier) in this paper are supported by CIC. The thesis can be divided into three parts：
The first part is on the design and implement of a high added efficiency power amplifier for W-band applications in 90nm CMOS technology. In this circuit, the fourth stages are implemented with single device common-source topology. which have better linearity and lower power consumption. The third stage using Y-shaped power divider/ combiner architecture with two output power. The fourth stage using Dual Y-shaped power divider/ combiner architecture with four way output power. Achieve output power and power added efficiency improvements. The measured results show gain (S21) is 12±1.1dB, saturation output power (Psat) is 5dBm, max power added efficiency (peak PAE) is 0.7%, total power consumption is 248.36mW and the chip area (including test pads) is 0.996*0.988mm2. This circuit performs well in power added efficiency (PAE) and saturated output power, and there is Width band 3db bandwidth. In addition, its OP1dB and gain have improved.
The second part is based on a 94GHz power amplifier implemented in the 90-nm process for the W-band. In the circuit architecture, a three-level CMOS PA is proposed. In order to improve the proposed PA gain and maintain the good PAE performance and stability of the CS, the first stage adopts a positive feedback of a common-source configuration to ensure unconditional stability. To increase output power (Pout), the bidirectional CS gain stage uses a Y-splitter and synthesizer, and two four-way CSs employ a double Y-splitter and a synthesizer for the last two stages of the PA. The gain of the circuit (S21) is 15.6 ± 1.1dBm, the saturation output power (Psat) is 14dBm and the maximum power added efficiency (PAE) is 7.7%. The power consumption of the circuit is reduced and the gain is kept relatively good, and the linearity of the whole circuit Boost, excellent performance in Gain, Psat, OP1dB and PAE.
The last part of the 90-nm power amplifier designed at 94GHz millimeter-wave frequency has significantly reduced transistor power gain with increasing frequency. The most advanced CMOS power amplifier commonly used in multistage cascode (CS) amplifier topologies enhances the gain band. With a new design 4-way Wilkinson divider all input and output to 50 ohms, this design can reduce the area consumption. Using Sonnet to design the microstrip line and optimized to achieve low loss at 94GHz, the PA unit section uses a CS amplifier stacked in three stages as an amplification function. To increase output power (Pout) and PAE, a bi-directional CS gain stage With a Y-splitter and synthesizer, not only can the area be reduced,but the optimum output power and PAE can be achieved with for Pout & PAE for load-pull simulation. The gain of the circuit (S21) is 12.6 ± 1.1dBm, the saturation output power (Psat) is 15.8dBm and the maximum power added efficiency (PAE) is 8.4%.
In this paper, circuit research has high gain, high output saturation, and high PAE. Input and Output have is matching. It can be applied to 77~81 GHz automotive radar and 94 GHz cloud imaging radar system.

並列關鍵字

Power Amplifier (PA) ； Power Added Efficiency (PAE) ； Saturation Output Power (Psat) ； W-band ； cascode ； Y-shaped divider/combiner ； Dual Y-shaped divider/combiner ； Marchand Balun ； common source ； Width ban

參考文獻

[1] Behzad Razavi, “RF Micorelectronics 2nd Edition,” Prentice-Hall,2011.

[2] David M.Pozar, “Microwave engineering,” John Wiley & Sons,Inc.

[3] CIC訓練課程(C604), “Power Amplifier Design and Simulation using ADS:Training Manual”, pp.54, July-2010

[4] Behzad Razavi, “RF microelectronics,” Prentice-Hall PTR, 1998

[5] 陳科后(2004).The Design and Implementation of Power Amplifier, Low Noise Amplifier and Wideband Amplifier. Unpublished master dissertation, National Chi-Nan