21~27 GHz 汽車雷達系統之CMOS 超寬頻接收機 前端設計與實現

Design and Implementation of 21-27 GHz CMOS UWB Receiver Front-ends for Automatic Radar Systems

陳永親(Yung-Chin Chen)

指導教授 ： 郭耀文

共同指導教授 ： 林佑昇(Yo-Sheng Lin)

國立暨南國際大學/科技學院/電機工程學系/碩士(2011年)

https://doi.org/10.6837/NCNU.2011.00185

摘要

本論文以CMOS製程實現射頻前端接收電路為目標，操作頻率在超寬頻頻帶以及21~27GHz，並以設計低雜訊放大器為主，研究主題分為三部分:

第一部分為應用在超寬頻低雜訊放大器，利用台積電0.18 mm CMOS 製程技術來實現。本研究使用一級的inverter加上一級common source的技術來完成此電路，且在第二級common source上使用Inductive Shunt Peaking，以期達到寬頻、低雜訊、低功耗且輸入輸出皆匹配的低雜訊放大器。量測結果:在3~10 GHz的頻帶中S11的耗損皆在-10 dB以下，S22的耗損皆在-9.7 dB以下，在S21的增益方面為12.47±3.32 dB，在5GHz時的增益下降可能是因為傳輸線的匹配不合所導致。晶片面積為0.34 mm2，電路功率消耗方面為16.9 mW。

第二部分為應用在24 GHz短距離汽車防撞雷達系統的超寬頻低雜訊放大器，利用台積電0.18 mm CMOS 製程技術來實現。為達到較高增益，此架構使用四級電路，第一級和第二級為共源級放大器，第三級使用則採用電流共用技術來降低功耗，來減少供應電壓已達到較低功耗，並使用T型匹配使輸出端匹配達到一個良好的結果。量測結果: S11的耗損皆在-12.52 dB以下，S22的耗損皆在-12.97 dB以下3dB增益頻寬為7.3 GHz為26.5~33.8 GHz，最低雜訊為4.3 dB在25 GHz，電路功率消耗為36.67 mW，晶片面積為0.77 mm2，此結果適合應用於需要高解析度的雷達系統。

最後在第三部分學生設計了兩個射頻前端接收機之電路，包含低雜訊放大器及混頻器所組成，低雜訊放大器方面學生設計一個採用了兩級串接就可達到超寬頻和低功耗，在混頻器上分為雙端平衡Gilbert及雙閘極混頻器做介紹，其中在雙閘級混頻器為第一級使用穩流和第二級使用疊接方式，使其有低電流消耗和較大增益，另外在電路方面學生使用了電容做為低通濾波器，可以有效的降低RF跟LO端信號對輸出的IF端訊號的影響，提升其隔離度。量測結果:隔離度LO_IF為-47 ~ -52.3 dB、LO_RF為-55 ~ -70.5 dB、RF_IF為-35.5 ~ -45.4 dB，且三端交會點(IIP3)為-25.5 dBm，轉換增益為20.2±2.2 dB，此電路在功率消耗方面只有16.41 mW。

在第二顆電路中，雙端平衡Gilbert混波器使用瑪遜巴倫來達成LO端的開關所需要的相位差且使用電流注入技術和共振電感來達到較寬頻的轉換增益，在轉導級的設計學生嘗試一種新的單端信號輸入方式，此方式可以有效的減少Noise Figure和功耗，量測結果:此電路操作在21~27 GHz時，轉換增益為12.89~16.77 dB，Noise Figure在21~25.5 GHz時皆不超過7dB且三端交會點(IIP3)為-15 dBm，而電路消耗功率為24.12 mW。此兩電路皆採用台積電0.18 mm 1P6M互補式金氧半製程實現。此兩電路結果適合應用於21~27 GHz汽車雷達系統之CMOS超寬頻接收機。

關鍵字

低雜訊放大器 ； 24GHz 短距離汽車防撞雷達 ； 前端電路 ； 電流再利用 ； 混頻器 ； 瑪遜巴倫

並列摘要

The thesis mainly uses CMOS process technology to implement the RF receiver front-end circuit, operating frequency at 21~27 GHz and UWB system, study the theme can be divided into three parts：

In the first part, application at UWB low noise amplifier, use the TSMC 0.18 mm one-poly-six-metal (1P6M) CMOS process. This study uses two stages of the inverter and the common source. This circuit uses Inductive Shunt Peaking technology at second stage, which to achieve wideband, low Noise Figure, low power consumption and has good impedance matching. The measured results: S11 is lower than -10 dB over 3.1~10.6 GHz and S22 is lower than -9.7 dB over 3.1~10.6 GHz; S21 is 12.47±3.32 dB. Except for the gain was down after 5 GHz. We conjecture that the microstrip line doesn’t match for UWB frequency. The chip area only has 0.34 mm2, it total power is consumed 16.9 mW

In the second part, the low-noise amplifier which is implemented by the TSMC 0.18 mm CMOS process can be used for a 24 GHz short-range automotive collision avoidance radar system. In order to obtain a high power gain, we used four stages that conjugate matching techniques between each stage. The first stage and the second stage are common source amplifiers. Simple topology at first stage can achieve low Noise Figure. The third stage uses the Current-reuse technique is adopted and the fourth stage to reduce power dissipation. The measured results: This LNA have flat gain 12.75±1.5 dB gain at 26.5 ~ 33.8 GHz, input/output return loss less than -12.52/-12.97 dB and lowest Noise Figure 4.3 dB at 25 GHz. The chip power consumption is 36.67 mW and area is 0.77 mm2. The results show that the LNA is suitable for high resolution radar systems.

The third part is applied to the receiver of front-end. The 21~27 GHz front-end circuits are implemented in a TSMC 0.18 mm CMOS technology. The circuit includes LNA and Mixer. The low noise amplifier both use cascode to accomplish width band and low power. In this section we introduce two type mixers, dual-gate mixer and double-balance mixer. The dual-gate Mixer is utilized on the stable current method in the first stage and cascode method in the second stage, which can achieve lower current consumption and larger gain, Another, we use a shunt capacitance and resistance for a low pass filter to filter out high frequency in the mixer, which can decrease the leakage LO to IF and RF to IF. The measured results: RF to IF isolation of -35.5 ~ -45.4 dB, LO to IF isolation of -47 ~ -52.3 dB, and LO to RF isolation of -55 ~ -70.5 dB, third-order intercept (IIP3) of 25.5 dBm, Conversion gain of 20.2±2.2 dB and the front-end only consumed 16.41 mW power consumed.

Another front-end is composed of LNA and double-balance mixer. In the mixer, the current bleeding technique and resonat inductance to achieve wideband conversion gain and low noise, Marchand balun to achieve the needed phase difference at LO port. We propose the type to drive the double-balance mixer by single-signal and the type can reduce the transistor’s noise and the power consumption. The measured results: RF frequency is 21~27 GHz, IF frequency is 100 MHz, LO frequency is 21.9~26.9 GHz. This front-end circuit is achieved max conversion gain of 16.77 dB at 24GHz. Besides, Measured S-parameter is achieved S11 of -8.43 ~ -19.08 dB, S33 of -10.34 dB, min Noise Figure of 5.96 dB, and third-order intercept (IIP3) of 15 dBm. Power consumption of front-end circuit is 24.12 mW. Chip area is 1.178 mm2 including the test pads. There 21~27 GHz front-end circuits of overall receiver are can be implemented.

並列關鍵字

low noise amplifier ； 24 GHz short-range radar system ； front-end ； current-reuse ； mixer ； Marchand balun

參考文獻

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