- 學位論文
19-29 GHz CMOS 接收機前端電路與八位元類比數位轉換器之設計與實現
Design and Implementation of 19-29 GHz CMOS Receiver Front-End and an 8 bit Analog-to-Digital Converter
摘要
本論文以CMOS製程實現接收機之前端電路，共分為兩大部分：應用於接收機19~29GHz之低雜訊放大器與一8位元類比數位轉換器的電路模擬與與實現。 第一部分為應用在19~29GHz的低雜訊放大器，利用台積電0.18μm CMOS製程技術來實現。本研究第一級電路使用Common Source的放大器結構，其目的為提供低頻的增益以及寬頻的匹配網路，適當選擇電晶體及傳輸線，可調整其gain的平坦度以及S11的匹配，且也與雜訊的高低有很大的關係；此LNA特色就是在第二級CasCode的電晶體M2及M3中間加入了電感L4，由於Cascode本身寄生電容會影響電路特性以及頻寬不足於是學生使用L4來共振雜散電容，使得增益以及平坦度有所提升。量測結果:在19~29GHz頻帶中S11 的耗損在-5~-16dB，S22耗損皆在-7以下，在S21增益方面為8.63±0.21dB，原因是在輸入端由於傳輸線匹配不合以至於S11損耗在-10以上；此電路消耗功率為8.49mW。 第二部分為一8位元類比數位轉換器，此電路同時也是利用台積電0.18μm CMOS製程技術來實現。此ADC設計為一8bit輸出，雙時脈輸入，弦波訊號由取樣保持電路輸入而保持取樣電路採用SAR端的重置時脈，位移暫存器產生的時脈調節取樣與保持的時間，保持輸出訊號在比較器一端維持一直流電壓而比較器另端為系統回授訊號來自DAC的訊號，時脈控制來自4個flip-flop電路產生除16的時脈，單一flip-flop為一個除2電路故4個串接可形成除2、4、8、16的電路在由一個and閘將訊號集成一個週期為16的時脈；Dac是採用傳統的電容陣列的架構，在此較特別的是開關陣列採用了 inverter 而非傳統的 transmission gate，這種作法有個好處是可以根據電容大小來決定充電速度， 這是因為在給相同的電壓下，大電容的充電速度一定比小電容的充電速度慢，而這種時間差會造成 sar 或 comparator 的不匹配性，進而影響到 INL/DNL。 因此可利用在大電容時 inverter 的並聯數目多來增加充電速度，而小電容時 inverter 的並聯數目少來降低充電速度，以希望達到大小電容之間的充電速度相同。電路架構由取樣保持電路、比較器電路、緩衝及維持輸出電路、時脈控制電路、邏輯控制電路、數位類比轉換器電路。此一8位元逐漸趨近式類比數位轉換器輸入為3kHz的訊號時脈為1MHz。
並列摘要
In this thesis, we using CMOS process to implement receiver front-end circuit, and divided into two part: a 19~29GHz Low Noise Amplifier applied to receiver system and an 8-bit Analog-to-Digital Converter simulation and implement. The first part is a 19~29GHz Low Noise Amplifier applied to receiver system, and we use 0.18μm CMOS technology provided by TSMC. In this study, the first stage circuit uses the Common Source amplifier structure, which aims to provide low-frequency gain and broadband matching network. Appropriate choice of the transistor and transmission line will adjust its gain flatness and S11 match, and also have a great relationship with the level of noise. The characteristics of this LNA is the second stage, we using a cascode structure and joined a inductor L4 between M2 and M3, because of Cascode itself parasitic capacitance will affect the circuit characteristics, as well as insufficient bandwidth so we use L4 to resonance stray capacitance, it could improve gain and flatness. Measurement results: at 19 ~ 29GHz S11 is -5 ~-16dB, S22 are less than -7 and the gain is 8.63 ± 0.21dB, reason for S11 higher than -10 is the transmission at the input had not matching well; this circuit power consumption is 8.49mW. The second part is an 8-bit analog to digital converter, this circuit is also using 0.18μm CMOS process technology provided by TSMC. The ADC is designed for an 8 bit output, dual time clock input, the sinusoidal signal from sample and hold input and maintaining for system working is controlled from SAR reset clock, the shift-generator produce a series clock to control sampling time and hold signal time, the comparator is differential input, signal is from sample and hold output and DAC output. Clock control from four flip-flop circuit and in addition to 16 clocks, a single flip-flop circuits as an addition to the two so the 4 cascaded to form in addition to the 2, 4, 8, 16, at last we using a AND gate to produce a 16 clock of a period; Dac is the traditional architecture of the capacitor array, in this particular switch array using the inverter instead of the traditional transmission gate, this approach benefit is based on the capacitor size to determine the charge rate, This is because in same voltage, the charging speed of the large capacitor must be slower than small capacitor, and these inaccuracy may cause SAR or comparator matching error to cause INL/DNL, so the large capacitor we could use the number of multi-inverter parallel to increasing charge time, and using less number of multi-inverter parallel to decrease charge time, to make the same time between large and small capacitor charge time. The SAR A/D Converter architecture is constitute by sample and hold circuit, comparator circuit, the buffer and maintain output circuit, the clock control circuit, the logic control circuits, digital-to-analog converter circuit, this 8-bit A/D Converter input signal of 3kHz clock is 1MHz.
參考文獻
延伸閱讀
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