使用變壓器架構之24 GHz CMOS 功率放大器

24 GHz Transformer Based CMOS Power Amplifier

王志誠(Chih-Cheng Wang)

指導教授 ： 黃建彰

共同指導教授 ： 蔡政翰

元智大學/電機通訊學院/通訊工程學系/碩士(2009年)

https://doi.org/10.6838/YZU.2009.00045

摘要

本論文主要針對24-GHz 微波CMOS 功率放大器之研究設計，晶片製作使用國家晶片中心提供的標準TSMC CMOS 0.18 μm製程，內容包括研究毫米波單晶變壓器(Millimeter Wave Monolithic Transformers)及功率放大器(Power Amplifiers)的設計。首先專注於研究單晶變壓器，並且提出了功率結合及阻抗轉換的觀念來達到高功率輸出。此外，提出利用單晶微波及毫米波積體電路(Monolithic Microwave / Millimeter Wave Integrated Circuits, MMICs)技術所設計的功率放大器，分別設計在K 頻帶(24-GHz)，。電路採全積體化方式使用標準TSMC CMOS 0.18 μm製程製作完成，其模擬得到的功率輸出有20dBm，增益為16 dB，PAE約15%；而以目前CMOS製程技術，操作在此頻段下之功率放大器仍未有高達20dBm之研究。量測得到的功率輸出有16.4dBm，增益為6 dB，PAE約5%。最後探討實驗結果與模擬誤差原因及改進方式。

關鍵字

CMOS ； 功率放大器 ； k-bamd

並列摘要

This thesis presents a 24 GHz full-integrated power amplifier (PA) which designed and fabricated in the 0.18-μm 1P6M standard CMOS technology. This power amplifier is a 2-stage design using cascode configuration with the broadside transformers. The simulation shows the PA achieves the maximum output power of 20.3 dBm and OP1dB of 16.45 dBm, a power added efficiency (PAE) of 15.3%, and a linear gain of 16.5 dB when VDD is biased at 3.0 V. The measured results shows the maximum output power of 16.4 dBm and OP1dB of 12.68 dBm, a power added efficiency (PAE) of 5.3%, and a linear gain of 5.6 dB when VDD is biased at 3.0 V. The chip size is only 0.59 x 0.47 mm2.
Finally, the differences between simulations and measurement results are addressed with some possible improvement directions.

並列關鍵字

CMOS ； Power Aplifier ； k-band

參考文獻

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