5.8-GHz CMOS 射頻接收機前端電路研製

A 5.8-GHz CMOS RF Receiver Front-End

陳信宇(Sin-Yu Chen)

指導教授 ： 吳紹懋

元智大學/工程學院/電機工程學系/碩士(2002年)

摘要

以低成本、高度整合性之CMOS技術來設計射頻積體電路己相當成熟。然而需提升在目前常見之900MHz, 1800MHz與2.4GHz系統頻段下的資料傳輸頻寬與速率，因此位於U.S之FCC組織便提出了擁有300MHz頻寬之5GHz無線系統規格。
本論文設計一個5.8-GHz射頻前端接收機電路, 且以台積電 0.25μm的CMOS製程將之實現。低雜訊放大器經量測後擁有9.3 dB的順向增益(Forward Gain)及5.3 dB 的雜訊指數(Noise Figure)。而以開關式形態為基礎之降頻混波器，它提供了0 dB的轉換增益(Conversion Gain)、9 dB的雜訊指數而其輸入三階交叉點(IIP3)則為7 dBm並且此接收機加以應用一90度之延遲閂鎖迴路來壓制系統的鏡像訊號，可達到40 dB的鏡像壓制比(Image Rejection Radio)。

關鍵字

無線接收機 ； 低雜訊放大器 ； 降頻器 ； 鏡像消除接收機 ； 90度延遲閂鎖迴路

並列摘要

The low-cost and high-integration radio frequency (RF) integrated circuit design based on CMOS technology had been very mature. However, the transmission of data and voice requires more bandwidth than that is currently required in the unlicensed bands at 900 MHz, 1.8 GHz and 2.4 GHz. Therefore, the FCC in the U.S. has proposed 300 MHz of bandwidth in the 5 GHz band.
In this thesis, a 5.8-GHz receiver front-end has been designed and implemented with TSMC 0.25μm CMOS technology. The LNA is measured with 9.3-dB forward gain and 5.4-dB noise figure. The downconversion mixer based on the switch type exhibits a conversion gain of 0-dB, DSB noise figure of 9-dB and an IIP3 of 7-dBm. Besides, the receiver uses the 90-degree DLL circuit to suppress the image signal with the image-rejection radio (IRR) of 40-dB.

並列關鍵字

IEEE 802.11a ； LNA ； low noise amplifier ； downconversion mixer ； 90-degree delay-locked loop ； image-rejection receiver

參考文獻

[1] K. Pahlavan, A. Zahedi, and P. Krishnamurthy, “Wideband local access: Wireless LAN and wireless ATM,” IEEE Commun. Mag., pp. 34-40, Nov. 1997.

[2] A. Matsuzawa, “RF-SoC-Expectations and Required Condition,” IEEE Trans. on Microwave Theory and Tech., vol. 50, no. 1, Jan. 2002.

[5] A. A. Abidi, “Direct-conversion radio transceivers for digital Communications”, IEEE J. Solid-State Circuits, vol. 30, pp. 1399-1410, Dec. 1995.

[6] J. C. Rudell, J.-J. Ou, T. B. Cho, G. Chien, F. Brianti, J. A. Weldon, and P. R. Gary , “A 1.9GHz Wide-Band IF Double Conversion CMOS Receiver for Cordless Telephone Applications,” IEEE J. Solid-State Circuits, vol. 32, No. 12, Dec. 1997.

[7] S. Sampei and K. Feher, “Adaptive DC-offset compensation algorithm for burst mode operated direct conversion receiver,” in Vehicular Technology Society 42nd VTS Conf., Denver, CO, May 1992, vol. 1, pp. 93-96.