應用於微波及毫米波之 CMOS 寬頻及多頻帶積體電路設計

CMOS Wideband and Multiband Integrated Circuits for Microwave and Millimeter-wave Applications

陳憲穀(Hsien-Ku Chen)

指導教授 ： 呂學士

國立臺灣大學/電機資訊學院/電子工程學研究所/博士(2011年)

https://doi.org/10.6342/NTU.2011.10354

摘要

隨著適用於不同無線通訊標準及頻帶的增加，整合許多功能在同一晶片中已成為了趨勢。在此論文，應用於寬頻及多頻段的無線接收機前端及其頻率合成器電路設計技術已被設計及製作。內容包含在無線接收機前端中的低雜訊放大器、平衡非平衡轉接器以及混頻器，以及頻率合成器中的除頻器及壓控震盪器，進而衍生至多頻段接收器與多頻段頻率合成器電路的設計。此論文主要的目標為研發具有小尺寸、少功率及低複雜度的電路技術於一適用於多標準、多頻段的晶片之中。此外，其他適用於寬頻及多頻段的電路方塊如寬頻放大器、壓控震盪器以及注入鎖定式除頻器，也已被設計、分析並且實現出來。

以下將簡述本論文兩個主要貢獻電路的設計︰
第一個電路為“多頻段鎖相迴路”。一個毫米波多頻帶的鎖相迴路已被提出，此電路涵蓋 40、60 以及 80 GHz 等三個頻帶的應用。三個壓控震盪器分別操作於不同頻率並可輸入同一多頻段注入鎖定式除頻器，藉以打開其一的壓控震盪器當模態選擇器，其頻率訊號將對應於相對的除數，在多頻段注入鎖定式除頻器完成除頻。而鎖相迴路之回授電路包含: 一個具 256 除數的除頻電路、一個頻率相位偵測器、一個充放電泵，以及一個二階低通濾波器。此一多頻段鎖相迴路以一個 78 MHz 穩定訊號源作為參考頻率，它在三個模態的輸出功率皆大於 -9.5 dBm。在距離中心頻率 10 MHz 處的相位雜訊為 -103 dBc/Hz。整個鎖相迴路實現在 90 nm CMOS 製程並在 1.5 V 的電源偏壓下，其直流功率為 114 mW，其面積為 1.12 mm2。
第二個電路為“0.1~28 GHz 低雜訊放大器”。基於一電阻回授之疊接式寬頻低雜訊放大器已被提出。以一並-並回授電路組態結合 π-型匹配網路實現了一寬頻的輸入阻抗匹配，並利用串接在輸出的串聯電感來增加其操作頻寬並亦同時抑制其高頻的雜訊指數。理論的推導分析顯示出可利用具品質因素及阻尼係數的二次函數來描述寬頻的增益及雜訊指數。此寬頻電路實現在 90 nm CMOS 製程，其面積包含了測試墊片僅為 0.139 mm2。在 1.2 V 的電源偏壓下之直流功率為 21.6 mW，電性表現在頻帶 1.6-28 GHz 間，其輸入及輸出的折返損耗皆小於 -10 dB，平坦的增益響應為 9.6±1.1 dB，平坦的雜訊指數響應為 3.68±0.72 dB 。此外，此電路亦具極好 +4 dBm 的輸入三階交互調變點。此電路經理論推分析、模擬，以及量測結果皆有很好的一致性。

關鍵字

互補式金氧半 ； 接收器 ； 發射器 ； 鎖相迴路 ； 低雜訊放大器 ； 混頻器 ； 壓控震盪器 ； 頻率除頻器 ； 毫米波 ； 寬頻 ； 多頻段

並列摘要

To integrate many functions into the single device has become the tendency toward increasing of wireless standards and frequency bands with different applications. The technologies of wireless receiver front-end with the frequency synthesizer have been investigated into applying to wideband and multiband circuits in this dissertation. It includes both receiver front-end and frequency synthesizer. There are low-noise amplifiers (LNAs), baluns and mixers in receiver front-end. In frequency synthesizer, there are frequency dividers and voltage controlled oscillator (VCO). A multiband receiver with the frequency synthesizer is also investigated. The purpose of this dissertation is to investigate the circuit technology with small size, low power and low design complexity in a wideband and multiband circuit for the multi-standard wireless application. Besides, other building blocks for wideband and multiband radio system such as wideband LNA, VCO and injection-locked frequency divider (ILFD) are designed, analyzed and then implemented.
The introduction of two main contributions in this dissertation is described as follows:
The first one is “Multiband phase-locked loop (PLL)”. A millimeter-wave multi-band phase-locked loop (PLL) is presented, which covers 40, 60 and 80 GHz bands. Three VCOs corresponding to different frequencies are input to a multi-band injection locked frequency divider (M-ILFD) and switched on one at a time by a multiplexer as a band selector. The feedback loop embraces the following components: a chain of dividers with a fixed division-modulus of 256, a phase-frequency detector (PFD), a charge-pump (CP), and a 2nd order loop filter (LF). The PLL is clocked by a reference frequency of 78-MHz, and its output power is higher than -9.5 dBm. The phase noise is -103 dBc/Hz at an offset frequency of 10 MHz. With a supply voltage of 1.5-V, the entire PLL consumes 114 mW. The chip is implemented in a 90-nm CMOS technology and measures 1.12 mm2.
The second is “0.1~28 GHz low noise amplifier”. A wideband low-noise amplifier (LNA) based on the cascode configuration with resistive feedback. Wideband input-impedance matching was achieved using a shunt-shunt feedback resistor in conjunction with a preceding pi-match network, while the wideband gain response was obtained using a post-cascode inductor (LP), which was inserted between the output of the cascoding transistor and the input of the shunt-shunt resistive feedback network to enhance the gain and suppress noise. Theoretical analysis shows that the frequency response of the power gain as well as the noise figure (NF) can be described by second-order functions with quality factors or damping ratios as parameters. Implemented in 90 nm CMOS technology, the die area of this wideband LNA is only 0.139 mm2 including testing pads. It dissipates 21.6 mW power and achieves S11 below –10 dB, S22 below –10 dB, flat S21 of 9.6 +/- 1.1 dB, and flat NF of 3.68 +/- 0.72 dB over the 1.6-28 GHz band. Besides, excellent input third-order inter-modulation point (IIP3) of +4 dBm is also achieved. The analytical, simulated and measured results are mutually consistent.

並列關鍵字

CMOS ； receiver (RX) ； transmitter (TX) ； phase-locked loop (PLL) ； LNA ； mixer ； VCO ； frequency divider ； millimeter-wave ； wideband ； multiband

參考文獻

[1.1] S. Cherry, "Edholm's law of bandwidth," IEEE Spectrum, vol. 41, no. 7, pp. 58-60, July 2004.

[1.2] H. Singh, J. Oh, C. Y. Kweon, X. Qin, H. R. Shao, and C. Ngo, “A 60 GHz Wireless Network for Enabling Uncompressed Video Communication,” IEEE Communications Magazine, pp. 71–78, Dec., 2008.

[1.3] S. Pellerano, R. Mukhopadhyay, A. Ravi, J. Laskar, and Y. Palaskas, “A 39.1-to-41.6GHz Fractional- N Frequency Synthesizer in 90nm CMOS,” ISSCC Dig. Tech. Papers, pp. 484–630, Feb., 2008.

[1.4] C. Lee, and S. I. Liu, “A 58-to-60.4GHz Frequency Synthesizer in 90nm CMOS,” ISSCC Dig. Tech. Papers, pp. 196–596, Feb., 2007.

[1.5] J. Lee, M. Liu, and H. Wang, “A 75-GHz Phase-Locked Loop in 90-nm CMOS Technology,” IEEE J. Solid-State Circuits, vol. 43, no. 6, pp. 1414–1426, Apr., 2008.