毫米波CMOS平衡式帶通濾波器之設計

Design of Millimeter-Wave CMOS Balanced Bandpass Filters

廖彥寧(Liao, Yenning)

指導教授 ： 張盛富

國立中正大學/工學院/電機工程學系/碩士(2012年)

摘要

論文研製V-Band CMOS非平衡-平衡式(Single-ended to balanced)和全平衡式(fully-balanced)帶通濾波器。非平衡-平衡式和全平衡式帶通濾波器以彎折式三線步階阻抗模態共振器為基礎，加上地面浮升技術，在通帶內產生諧振模態，並設計輸入和輸出埠，達到輸出相位反差之效果，並設計傳輸零點，以增加禁帶拒斥值和共模拒斥比。
第一個晶片濾波器為CMOS 0.18-m 60 GHz非平衡-平衡式帶通濾波器，量測結果在55 GHz-65 GHz頻段內植入損耗為4 dB，輸入返回損耗優於14 dB，功率不平衡小於0.5 dB，相位不平衡小於3度，共模拒斥比大於25 dB，晶片面積為0.17 mm2 (不包含輸出入埠之探針片) 。第二個晶片濾波器為CMOS 90-nm 60 GHz非平衡-平衡式帶通濾波器，模擬結果在55-65 GHz通帶內，中心頻率為60 GHz，植入損耗為3.7 dB，反射損耗優於14 dB，頻帶為55 GHz - 65 GHz，功率不平衡小於0.3 dB，相位不平衡小於2度，共模拒斥比大於35 dB，不包含接觸片面積為0.04 mm2。第三個晶片濾波為使用TSMC90-nm CMOS製程，模擬結果在55 GHz-65 GHz頻段內植入損耗為4.4 dB，輸入返回損耗小於14 dB，共模拒斥比大於25 dB，不包含接觸片面積為0.132 mm2。量測結果與模擬結果符合，驗證本論文提出之彎折式三線步階阻抗模態共振器架構，以及地面浮升技術確實可以大幅縮小晶片面積，達到毫米單晶片系統的需求。

關鍵字

平衡式濾波器

並列摘要

This thesis investigated V-band single-ended-to-balanced and fully-balanced bandpass filters in CMOS technology. These balanced bandpass filters were designed based on three-line stepped-impedance resonator to obtain differential output phases and were incorporated with the ground plane reformation to minimize the circuit size. A transmission zero near passband was generated to enhance stopband suppression and common-mode rejection ratio.
Three CMOS V-band filters were designed. First, the CMOS 0.18-m single-ended-to-balanced bandpass has a measured insertion loss less than 4 dB and the return loss better than 14 dB in 55-65 GHz. The power imbalance is less than 0.5 dB and the phase imbalance is less than 3˚. The common mode rejection ratio (CMRR) is better than 25 dB. The chip size, without input and output GSG pads, is 0.171 mm2. Second, the 90-nm single-ended-to-balanced bandpass filter has a simulated insertion loss less than 3.7 dB and the return loss is larger than 14 dB in 55-65 GHz. The power imbalance is less than 0.3dB, and the phase imbalance is less than 2˚. The CMRR is better than 35 dB. The chip size, without input and output GSG pads, is 0.0398 mm2. The CMOS 90-nm fully-balanced bandpass filter has a simulated insertion loss less than 4.4 dB and the return loss better than 14 dB in 55-65 GHz. Third, the common mode rejection ratio is better than 25 dB. The chip size, without input and output GSG pads, is 0.132 mm2. These results demonstrate the proposed differential bandpass filtering configuration with ground plane reformation achieve high performances and a compact chip size.

並列關鍵字

Balanced Filter

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