- 學位論文
以65-nm CMOS製程製作應用於光通訊之收發器
Transceivers for Optical Communication in 65-nm CMOS Technology
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摘要
本論文中，提出了兩種以65奈米互補式金氧半製程製作的應用於光通訊的傳輸機，其包括一應用於雷射測距雷達之前端電路以及一應用於100-Gb/s乙太網路的2×25-Gb/s串行器/解串行器。 在雷射測距雷達中，其前端電路採用一雙位準的偵測方式來消除測距雷達本身的飄移誤差，並且使用了一校正電路來修正電壓偏移。此前端電路、光模組和時間數位轉換器可整合成一完整測距雷達，此測距雷達亦採用了一種調變頻率的演算法來達成更高的精確度，最後可達到小於3毫米的精確度，功耗為50毫瓦。 在2×25-Gb/s串行器/解串行器，串行器內包含了2^7-1偽二進位隨機訊號產生器、多工器以及前饋等化器，解串行器則有限幅放大器、資料時脈回復電路以及解多工器。此外，串行器和解串行器分別有其各自的時脈產生器。此組晶片經測試可達到小於小於10^-12的位元誤碼率，而串行器和解串行器則分別消耗300毫瓦和520毫瓦之功率。
並列摘要
In this thesis, two different kinds of transceivers for optical communication have been proposed, including a front-end circuit used in laser ranging radar and a 2×25-Gb/s serializer/desrializer (SERDES) for 100-Gb/s Ethernet. They are both implemented in 65-nm CMOS technology. In laser ranging radar, the front-end circuit adopts two-threshold method to eliminate walk error of the radar, and uses a calibration circuit to correct the voltage offset . The front-end circuit, optical component, and time-to-digital converter (TDC)can be integrated to a complete ranging radar, and the radar utilizes a modulated clock algorithm to improve accuracy. Finally, it achieves a accuracy of less than 3 mm and consumes 50 mW. In 2×25-Gb/s SERDES, 2^7-1 pseudo random binary sequence (PRBS) generator, multiplexer (MUX), and feed-forward equalizer (FFE) are implemented in serializer. The deserializer includes limiting amplifier, clock and data recovery (CDR) circuit, and demultiplexer (DMUX). Furthermore, serializer and desrializer have their respective clock generators. The chip-set can achieves BER < 10^-12, and consumes 300 mW and 520 mW in serializer and deserilizer, respectively.
參考文獻
[1] T. Ruotsalainen et al., “A Wide Dynamic Range Receiver Channel for a Pulsed
[7] Serial ATA. [Online]. Available: http://www.sata-io.org/
[8] PCI-SIG. [Online]. Available: http://www.pcisig.com/
[9] Behzad Razavi, Design of Integrated Circuits for Optical Communications, First Ed., New York: McGRAW-HILL, 2003.
286-287, June 2011.
延伸閱讀
- Shih, Y. N. (2010). 以65-nm CMOS 製程製作應用於背板通訊之有線收發器 [master's thesis, National Taiwan University]. Airiti Library. https://doi.org/10.6342/NTU.2010.10093
- Lee, I. T. (2013). 時脈產生器之分析與設計於65奈米CMOS技術 [doctoral dissertation, National Taiwan University]. Airiti Library. https://doi.org/10.6342/NTU.2013.10157
- Chiang, T. (2013). 使用 0.18-um CMOS 製程製作之射頻能量擷取器 [master's thesis, National Taiwan University]. Airiti Library. https://doi.org/10.6342/NTU.2013.01148
- 李紹義（2007）。以標準CMOS製程製作傳送/接收之接觸式射頻微機電開關〔碩士論文，國立臺北科技大學〕。華藝線上圖書館。https://www.airitilibrary.com/Article/Detail?DocID=U0006-2808200713143400
- 梁曉堯（2011）。Silicon integrated photonics for bi-directional optical transceiver module multiplexer〔碩士論文，國立清華大學〕。華藝線上圖書館。https://www.airitilibrary.com/Article/Detail?DocID=U0016-0805201213314150