利用電壓幫浦提升四電晶體記憶單元供壓與負字元線的低功耗靜態隨機存取記憶體

靜態隨機存取記憶體被廣泛應用在像是電腦中多核心中央運處理單元的第二級快取記憶體，高速交換器，路由器和高速網路伺服器的第三級快取記憶體等許多高速運算相關的緩衝存取記憶工作。以及液晶平面顯示器中驅動IC，系統單晶片及手機系統中的嵌入式應用。因為有著高速工作時脈和小型存取容量及較小的晶片面積等優點可以達到高度彈性與各種眾多整合性產品的系統應用。雖然六電晶體的記憶體單元被廣泛的使用在各種靜態記憶體電路中，但是因為先天上的架構造成需要佔據較大的晶片單位面積與功率消耗，為了達成小面積與低功耗低成本的設計，本論文中將採用四個電晶體的架構來組成記憶體單元。導因於半導體製程的演進，使得次微米正式進入到深次微米製程後，互補式金氧半電晶體元件的漏電流問題日趨嚴重，靜態功率消耗的設計與考量也成為了記憶體中一個重要的課題，本論文將利用負字元線的方法來抑制在次微米製程中的靜態次臨界漏電流而不使用任何特別的多臨界電壓製程。再藉由電壓幫浦稍稍增加一些電路消耗功率，換取瞬間提高記憶體單元中的供給電壓以得到更高的靜態雜訊邊限。同時，為了要有更高的系統整合度以及更符合低成本的大量製造原則，將採用互補式金氧半導體製程來設計與模擬，以期能設計出高效能且低功耗的靜態隨機存取記憶電路。本論文將提出一個記憶容量大小為1k，以四電晶體為記憶單元的低功耗靜態記憶體電路，利用電壓幫浦在資料讀取時瞬間，提高記憶單元供給電壓，來有效改善靜態雜訊邊限，並採用負字元線，來縮小記憶體電路在靜態待命時的閘極漏電流。最後，將會提出一個雙端輸入單端輸出，利用電流轉換電壓的電流感應放大器，並在單端輸出後方加上史密特觸發器，來幫助抑制位元線上的雜訊。本論文中所有電路均以台積電0.18微米互補式金氧半導體製程來設計與模擬，儲存大小為1k，靜態雜訊邊限為530毫伏特，靜態漏電流為0.082毫安培，電路功率消耗在待命，讀取與寫入分別為0.18毫瓦，9.43毫瓦與7.38毫瓦。

關鍵字

靜態隨機存取記憶體；電壓幫浦；低功耗

並列摘要

Static random access memory (SRAM) has its own name known loud and clear in the hood of the high speed memory applications. From the level 2 (L2) caches in the gigahertz multi-core central processing units (CPUs), level 3 (L3) caches in the high speed switches, hubs and network servers to the embedded uses such as the liquid crystal display (LCD) driver ICs, system-on-a-chips (SoCs) and cell phone integrations, SRAM works all. It aims to the field of the high speed data rate use in a rather smaller memory size in both memory capacity and die area with full of the flexibility and integrability. Despite the mostly adopted 6-T memory cell is so classic and seemingly flawless. When talking of the necessarily active area issue then is another story. Less is more, hence we assume the 4-T cell to be the memory core of our design. With the aid of the negative word line scheme, the dramatically increased sub-threshold leakage in the sub-micron technology is then effectively eliminated without using any special process fabrication technology. As to noise, boosting the cell supply voltage gains us a significantly static noise margin (SNM) improved with a little extra power penalty. Meanwhile, the CMOS technology is the chosen one for us with the higher-level system integration and lower-cost manufacturing requirement. Looking forward to be in the way of making it powerful but not power hungry. In this thesis, we propose a SNM improved, low power consumption 1k 4-T SRAM structure with the boosted cell power supply by the proposing voltage heap pump, and the negative word line scheme in order to minimize the stand-by gate leakage current. Further, by proposing a current to voltage type current sense amplifier with Schmitt trigger adds a little help to fight for the noise interference. Simulated in the TSMC 0.18um CMOS process, the SNM of this 1k SRAM circuit is 530mV with the stand-by leakage current about 0.082mA, and consumes only 0.18mW, 9.43mW and 7.38mW in stand-by, read and write, respectively.

並列關鍵字

SRAM ； Heap Pump ； Low Power

參考文獻

[1] Kiyoo Itoh “VLSI Memory Chip Design” Itoh, Kiyoo, 1941-

Berlin ; New York : Springer, c2001

[2] Fang-shi Lai and Chia-Fu Lee ”On-Chip Voltage Down Converter to Improve SRAM Read/Write Margin and Static Power for Sub-Nano CMOS Technology”. IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 42, NO. 9, SEPTEMBER 2007

[3] Chua-Chin Wang, Ching-Li Lee, and Wun-Ji Lin “A 4-kb Low-Power SRAM Design With Negative Word-Line Scheme”. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 54, NO. 5, MAY 2007

[5] K. Nii, et al. “A low power SRAM using auto-backgate-controlled MT-CMOS”. In International Symposium on Low Power Electronics and Design, pp.293-298m 1998.

國際替代計量

利用電壓幫浦提升四電晶體記憶單元供壓與負字元線的低功耗靜態隨機存取記憶體

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