- 學位論文
具超晶格結構之高效能氧化銦/氧化鎵透明薄膜電晶體之特性研究
High Performance Transparent Thin Film Transistors Based on Indium Oxide/Gallium Oxide Super-Lattice Structure
摘要
本論文研究以射頻濺鍍法於室溫環境下製作氧化銦/氧化鎵透明薄膜電晶體的方法。藉由調控氧化銦通道的成長條件，並以傳輸線模型量測其電阻率與金屬-半導體接觸特性，發現當氧化銦通道電阻率約介於4.4×10^4 Ω-cm至6.56×10^5 Ω-cm之電晶體的特性最為穩定。對於閘極絕緣層而言，吾人以電漿輔助化學氣相沉積法於低溫下成長氮化矽，考量到金屬與氧化銦功函數差距，我們使用鉬(Mo)做為電晶體的汲極、源極與閘極接觸電極，成功製作出特性穩定的空乏型氧化銦薄膜電晶體。其通道長/寬比為8 um/80 um，元件之臨界電壓約-2.2 V、開/關電流比1.6×10^6、元件之次臨界擺幅與場效載子遷移率分別為1.3 V/decade與1.98 cm^2V^-1s^-1。 接續前述之基礎研究，本論文於其後引入超晶格通道概念於薄膜電晶體製作中，以場通道結構設計來提升前述元件之操作特性。在室溫下，具此結構的氧化銦/氧化鎵薄膜電晶體具有相當理想之操作特性。其臨界電壓約4.5 V、電流開/關比從10^6提升至10^7、飽和電流30 uA (W/L=80 um/8 um)、元件之次臨界擺幅與場效載子遷移率分別為0.66 V/decade與0.3~1.02 cm^2V^-1s^-1。元件通道區穿透率於可見光波段 (350 nm-750 nm)間皆大於80 %。 此外，由C-V量測結果所示，本論文所探討的薄膜電晶體，其界面陷阱密度約10^12~10^13 cm^-2eV^-1，其移動缺陷相當密集約8.85×10^11 cm^-2。產生密集的介面陷阱密度與移動缺陷之原因可能是來自於低溫成長之氮化矽絕緣層，此為限制元件載子遷移率的原因之一。然而能在低溫下成長良好特性薄膜電晶體的特性，使本元件將可應用於軟性電子領域之各類光電電子元件的主動關關。
並列摘要
We report a fabrication method to realize transparent thin film transistors (TFTs) at room temperature using radio frequency (RF) sputtered In2O3/Ga2O3 materials. The transmission line method (TLM) was used to examine the relationship between the resistivity of oxide channels and the growth conditions. We note that the oxide TFTs with channel resistivity lying between 4.4×10^4 Ω-cm to 6.56×10^5 Ω-cm exhibit better transistor characteristics. The gate insulator was formed by a thin silicon nitride layer grown by plasma enhanced chemical vapor deposition (PECVD) at low temperature. Considering the work function difference between the metal and the indium oxide, We selected molybdenum (Mo) as the source, drain, and gate contact metals. For an In2O3 TFT with a channel length and channel width of 8 um and 80 um, the device is operated at a depletion mode with a threshold voltage of -2.2 V. The electrical characteristics also exhibit the following: an on-to-off current modulation ratio (Ion/Ioff) of ~1.6×10^6, a subthreshold swing (S) of 1.3 V/decade, and a field-effect mobility (uFE) of 1.98 cm^2V^-1s^-1. We further proposed a new device design by including a supper-lattice channel structure to improve the transistor characteristics at room temperature. Using incorporating an In2O3/Ga2O3 super-lattice channel structure, the transistor is shown to operate in an enhancement mode with a threshold voltage of 4.5 V. The device exhibits improved characteristics: with the on-to-off current modulation ratio (Ion/Ioff) increased from ~10^6 to 10^7, and the saturation current 30 uA (W/L=80 um/8 um). The subthreshold swing (S) and field-effect mobility (uFE) are estimated as 0.66 V/decade and 0.3~1.02 cm^2V^-1s^-1, respectively. All The TFT channels are transparent in visible wavelength (350 nm~750 nm) with transmittance over 80%. We further provide CV analysis to show that the interface trap density is 10^12~10^13 cm^-2eV^-1 for our TFTs, and the mobile charge density is 8.85×1011 cm-2. The reasons can be ascribed to the low temperature grown of silicon nitride. The high level mobile charge may be one of the reasons to limit the mobility of our TFT devices. However, the super-lattice TFTs offer good transistor characteristics to serve as candidate for active switch for flexible electronic applications.