應用於微波毫米波之低雜訊放大器與正交解調器之研製

Research of Low Noise Amplifier and I/Q Demodulator for Microwave and Millimeter-wave Applications

謝峻安(Chun-An Hsieh)

指導教授 ： 王暉

國立臺灣大學/電機資訊學院/電信工程學研究所/碩士(2013年)

https://doi.org/10.6342/NTU.2013.01333

摘要

本論文主要涵蓋三個研究方向：第一部分是對應用於天文計畫之中頻低雜訊放大器的探討。第二部分是提出一線性器去實現高頻低雜訊放大器的線性度改善。第三部分是V頻帶正交解調器之研製。
藉由準確地選擇電路架構，此低雜訊放大器在4-12 GHz系統規格之中頻頻帶內提供足夠的增益(24±4 dB)及出色的雜訊指數(1.3±0.3 dB)。為了更貼近實際應用中的情況，本章後半段呈現該電路在低溫下的量測結果。另外，也討論了電晶體及材料物理特性在低溫環境中的表現，並進一步地提出相對應的電晶體低溫小訊號模型，並成功地預測低溫下的電路表現。
在本文的第二部分提出了可以改善60 GHz低雜訊放大器之線性度的內建式線性器。在本設計中，採用分離式疊加的概念並仔細考慮額外的寄生效應，使之能操作於更高頻段。在本章中，以65-nm CMOS製程實現了兩個低雜訊放大器，分別是有加線性器與沒加線性器的版本。實驗結果顯示有加線性器的低雜訊放大器可以達成24-dB的增益及4.8-dB 的平均雜訊指數，與另一沒加線性器的電路相似。另外，加上線性器後，在60 GHz附近的頻率，三階交互失真雜訊功率的抑制皆可以達到14 dB。
最後本文使用65-nm CMOS製程去實現一個由次諧波混頻器所組成的正交解調器。因為使用較少的電晶體去實現次諧波混頻，因此能夠達成較低的本地震盪源訊號及較小的晶片尺寸。量測結果顯示此電路有 -11-dB的轉換增益以及足夠的頻寬去進行高資料量的傳輸。

關鍵字

低雜訊放大器 ； 互補式金屬氧化物半導體 ； 毫米波 ； 線性化 ； 正交解調器 ； 次諧波混頻器

並列摘要

This thesis consists of three parts: in the first part, the IF LNA design for astronomical application is investigated; in the second part, the linearity improvement of LNA at high frequency is studied; in the third part, the implementation of demodulator at 60 GHz is researched.
By properly choosing circuit architecture, the LNA demonstrates sufficient gain performance, 24±4 dB, and excellent noise figure,1.3±0.3 dB, from 4 to 12 GHz which is the IF bandwidth of the system. The cryogenic performances of the circuit are also presented. In addition, the behavior of 0.15-μm pHEMT devices in cryogenic temperature is discussed.
A built-in linearizer is proposed to improve the linearity of LNA operating around 60 GHz. The concept of derivative superposition is applied and the parasitic effects are considered carefully in this work. Two versions LNAs, with and without linearizer, are demonstrated in 65-nm CMOS process. The experiment results of the linearized LNA show 24-dB gain and 4.8-dB averaged noise figure which are similar to the other LNA. After adding the linearizer, the reduction of IM3 distortion power is roughly 14 dB in various frequencies around 60 GHz.
An I/Q demodulator based on sub-harmonic mixer is presented in 65-nm CMOS. With fewer transistors to compose the mixing core, lower LO driving power and smaller area can be achieved. The measurement results express -11-dB conversion gain and enough bandwidth for high data rate transmission.

並列關鍵字

low noise amplifier ； CMOS ； millimeter-wave ； linearization ； I/Q demodulator ； sub-harmonic mixer

參考文獻

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