在本論文中,使用穩懋半導體的0.15微米砷化鎵高速電子遷移率電晶體製程設計一個於20至48 GHz的低雜訊放大器,這個低雜訊放大器的量測結果與穩懋半導體提供的元件模型模擬符合。 為了設計於穩懋半導體的0.1微米砷化鎵高速電子遷移率電晶體製程的放大器,完成穩懋半導體的0.1微米砷化鎵高速電子遷移率電晶體製程的Angelov模型,這個模型可以用於電晶體的小訊號及大訊號參數模擬。 此外,用穩懋半導體的0.1微米砷化鎵製程設計了一個於27至45 GHz的低雜訊放大器,而其量測的結果與利用該模型所模擬的結果近似。因此此模型可以在未來的設計中被採用。另外,為了減低熱雜訊的影響,此低雜訊放大器也在約20K的低溫下量測,結果顯示了較常溫大幅降低的雜訊溫度。電晶體的測試元件同樣也在低溫下量測,並淬取小訊號模型與常溫模型做比較。發現0.1微米砷化鎵在低溫下的增益並沒有提高,但雜訊溫度明顯降低。 因應日益成長的高頻寬頻放大器,利用0.13微米矽鍺異質接面雙極電晶體製程,實現一個75至140 GHz的寬頻放大器,此放大器使用疊接式架構獲得較大的增益,並利用電流鏡偏壓來精準控制流入基極的電流,而量測出的小訊號參數也與模擬結果大致上相似。
In this thesis, an LNA from 20 to 48 GHz in WIN 0.15-μm pHEMT process is designed and measured. The measurement results agree well with the simulation by the models provided by WIN. For designing amplifiers in WIN 0.1-μm pHEMT, the Angelov model of WIN 0.1-μm pHEMT process is generated, and this model can be used in small signal and large signal simulation. An LNA from 27 to 45 GHz in WIN 0.1-μm pHEMT is designed. The measurement results of the LNA agree with the simulated results using the model. Besides, to eliminate the thermal noise, the devices are operated in cryogenic temperature. The small signal model in cryogenic temperature is established. The noise temperature of the LNA in cryogenic operation is much lower than that at room temperature. The test transistor is also measured at cryogenic temperature, and the small-signal model is extracted to compare with that at room temperature. It is observed that the gain of the LNA in WIN 0.1-μm pHEMT does not increase at cryogenic operation, but the noise performance is enhanced substantially. For D-band applications, the 0.13-μm silicon-germanium heterojunction bipolar transistor is used to design a broadband amplifier from 75 to 140 GHz. The cascoded structure is implemented to achieve high gain, and the bias is realized by the current mirror to accurately control the base current.