使用CMOS製程之60 GHz WiGig接收機與D頻段訊號源設計

Design of 60 GHz WiGig Receiver and D-Band Signal Source in CMOS Process

張譽騰(Yu-Teng Chang)

指導教授 ： 盧信嘉

國立臺灣大學/電機資訊學院/電子工程學研究所/博士(2019年)

https://doi.org/10.6342/NTU201903653

摘要

本論文的研究主題是V頻帶WiGig低功耗接收機和使用矽透鏡封裝之D頻段訊號源設計。本V頻帶WiGig低功耗接收機擁有足夠的增益和較低的直流功耗，並可藉由內建功率偵測器偵測功率大小，切換不同的增益來提高線性度，以避免接收機增益飽和。在該系統中，低功耗可調式增益低雜訊放大器和混頻器相當重要，我們採用電流再利用技術來節省直流功率，也可避免可調式增益低雜訊放大器之阻抗變化。最後，再透過基頻放大器補足接收機增益以達到預期的規格。對於毫米波D頻段訊號源，本論文將會說明如何設計D頻段訊號源電路，並簡述天線和矽透鏡封裝之理論和模擬。一般基頻之高頻訊號源設計，將會遇到可調頻率範圍和交直流轉換效率之問題，故本論文採用切換式變壓器，來改善輸出頻率範圍。為了解決效率問題，我們設計70 GHz之振盪器串接倍頻器以產生140 GHz訊號源，並改善交直流轉換效率，以降低直流功耗。最後，在將140 GHz訊號源與晶片天線整合，然後再透過矽透鏡封裝後，來提升D頻段訊號源的EIRP和效率。
本論文之電路採用台積電40 nm LP CMOS製成來實現低功率之V頻帶接收機之設計，此電路採用直接轉換接收機架構，接收機包含可調式低雜訊放大器、次諧波混頻器、功率偵測器和基頻放大器。為了節省直流功率，可調式低雜訊放大器和次諧波混頻器採用電流再利用技術來實現，而功率偵測器採用平方律之架構來偵測功率以控制可調式低雜訊放大器，並使用Cheery-Hooper放大器做為基頻放大來補足增益。在60 GHz時，其量測的頻寬可以同時涵蓋四個通道。當電源電壓為1.1 V時，其直流功耗為31.5 mW。在不同的增益下，量測的2-dB增益頻寬範圍在60 GHz附近時，可大於10 GHz。在高增益模式下，每一個通道的量測到2 dB的頻寬皆大於2 GHz，每個通道的最高增益也大於30 dB。在切換增益時，接收機的增益分別為30.89 / 26.05 / 22.65 / 18.64 dB，而且四個通道的平均IP1dB分別為-42.55 / -37.65 / -33.28 / -29.23 dBm。
另外，本論文的電路採用台積電40 nm GP CMOS製成來實現低功率之D頻段訊號源設計，為了擴展調諧範圍，我們採用切換式變壓器改變其耦合係數做為頻率的粗調，而由變容器進行頻率的微調。此次140 GHz訊號源是由70 GHz 的VCO與頻率倍頻器串接所組成的。我們採用開槽環型天線來解決晶片佈局金屬密度限制問題，再將矽透鏡與晶片封裝後，進而提高晶片天線的增益和EIRP。在電源電壓為1 V時，其直流功耗為51 mW，振盪器量測到的頻率範圍約為14.5％，即從122.9 GHz至142.9 GHz。在142 GHz時，峰值輸出功率和峰值效率分別為-2 dBm和1.74％。在天線方面，量測的輸入反射係數小於-10 dB之頻率範圍是從140 GHz到175 GHz。當透鏡的半徑為2.5 mm，5 mm和8 mm時，訊號源量測所得的最高的EIRP分別為5.63 / 11.33 / 16.94 dBm。

關鍵字

波束成形 ； 電流再利用技術 ； 等效全向輻射功率 ； 轉導促進技術 ； 毫米波 ； 晶片天線 ； 透鏡封裝 ； 訊號源 ； 開槽環型天線 ； 切換式變壓器 ； 次諧波

並列摘要

This dissertation presents the design of a low power V-band direct-conversion receiver for WiGig applications and a lens-integrated D-band signal source. The advantage of the power V-band receiver is the receiver has sufficient gain and low dc power consumption. In addition, power detector is also integrated to generate a digital signal to switch to different gain to improve linearity and avoid receiver from saturation. We use the current re-used technique to save dc power consumption for the VGLNA and mixer. Moreover, it can also avoid impedance variation during VGA gain switching. Finally, we use the baseband amplifier amplifies to achieve the desired conversion gain. For the millimeter-wave D-band signal source, this dissertation will discuss how to design the D-band signal source circuit, and briefly describe the theory and simulation of the on-chip antenna and Si lens package. In general, the higher fundamental frequency signal source will encounter the tuning range and ac/dc conversion efficiency. Therefore, we use a switching transformer to improve the output frequency range. In order to solve the efficiency problem, we design a 70 GHz oscillator and cascade with a frequency doubler to generate a 140 GHz signal to improve efficiency and save dc power consumption. Finally, the 140 GHz signal source is connected with the on-chip antenna, and then packaged with Si lens to improve the EIRP and efficiency of the D-band signal source.
The four-channel low power receiver is realized in the 40 nm LP CMOS process. We adopt a direct conversion receiver for this design and the receiver includes the variable gain low noise amplifier, sub-harmonic mixer, power detector, and baseband amplifier. In order to save dc power, the variable gain low noise amplifier and sub-harmonic mixer are implemented by current re-used technique. The power detector uses a square law architecture to detect power and control the variable gain low noise amplifier. Finally, we use the Cheery-Hooper amplifier as the baseband amplification to achieve sufficient gain. The total power consumption is 31.5 mW with 1.1 V supplied voltage. Under different gain states, the gain bandwidth range is large than 10 GHz around 60 GHz. The measured 2-dB bandwidth of each channel is greater than 2 GHz, and the peak gain is also large than 30 dB at high gain mode. The gain of the receiver are 30.89/26.05/22.65/18.64 dB and corresponding to the measured average four channel IP1dB of -42.55/-37.65/-33.28/-29.23 dBm under different gain states.
The D-band signal source is realized in the 40 nm GP CMOS process. In order to extend the tuning range, we adopt the switching transformer to change the coupling coefficient to be the coarse frequency tuning and the varactor for fine frequency tuning. We cascade the 70 GHz VCO with a frequency doubler to generate an output signal at 140 GHz. We adopt the on-chip slot ring antenna to overcome the metal density limitation of layout, and the Si lens is used to improve the gain and EIRP of the on-chip antenna. The measured tuning range of VCO is 14.5 % which is from 122.9 to 142.9 GHz. At 142 GHz, the peak output power and peak efficiency are -2 dBm and 1.74 %, respectively. The return loss of the slot ring antenna is better than 10 dB from 140 to 175 GHz. When integrated with lenses with radiuses of 2.5 mm, 5 mm and 8 mm, the measured peak EIRP of the signal source is 5.63/11.33/16.94 dBm at different lens sizes, respectively. The total dc power consumption is only 51 mW for 1 V supplied voltage.

並列關鍵字

beamforming ； current-reused technique ； EIRP ； gm-boost ； millimeter wave ； on-chip antenna ； integrated silicon lens ； signal source ； slot ring antenna ； switching transformer and sub-harmonic

參考文獻

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