三相四線併網換流器之分離電容電壓數學模型推導與驗證

Derivation and Verification of Mathematical Model for Split-Capacitor Voltages in Three-Phase Four-Wire Grid-Tied Inverters

張哲維(Che-Wei Chang)

指導教授 ： 陳耀銘

國立臺灣大學/電機資訊學院/電機工程學研究所/碩士(2019年)

https://doi.org/10.6342/NTU201903756

摘要

本論文推導了一個能描述三相四線式併網換流器中分離電容電壓之數學模型，由於類比轉數位訊號誤差會導致分離電容電壓的不平衡，推導此數學模型的目的在於釐清類比轉數位訊號誤差對分離電容電壓之影響。當數位訊號處理器在偵測輸出電流之回授訊號過程中，類比轉數位訊號過程中容易產生誤差，即使輸出電流已受良好的調節，此誤差仍會使得數位訊號處理器接收到不準確的輸出電流值，在此情況下，輸出電流將因此而產生偏移並進一步造成分離電容電壓的不平衡。最終，不平衡的分離電容電壓將因觸發直流端電壓保護而使換流器被迫停機，或是損害直流端電容器的壽命。
為了驗證上述之分析，本論文推導了一個能精準預測分離電容電壓之值及波形之數學模型。由於三相四線式換流器之基本架構為三個單相半橋式換流器所組成，因此數學模型將首先以單相半橋式電路架構進行推導。接著，數學方程式能延伸至三相四線式電路架構進而推導出分離電容電壓之數學模型。本論文將會詳細介紹並說明由類比轉數位訊號誤差造成不平衡分離電容電壓之機制，及數學模型推導之細節，並將由電腦模擬及一組3kVA原型機之實驗結果來驗證推導出的數學模型之準確性。

關鍵字

數學模型 ； 三相四線式併網換流器 ； 分離電容電壓 ； 類比轉數位訊號誤差

並列摘要

This thesis derives a mathematical model for the unbalanced split-capacitor voltages caused by the analog-to-digital converter (ADC) signal deviation in three-phase four-wire (3P4W) grid-tied inverters. The ADC is a system that converts an analog signal into a digital signal and the ADC signal deviation can occur easily while utilizing digital signal processor (DSP) to sense the feedback signal of output current. As a result, the DSP will then receive an inaccurate value of the output current even though the output current has been well regulated. The ADC signal deviation will mislead the DSP to generate an offset on the output current and further causes the variation of split-capacitor voltages. Eventually, the unbalanced capacitor voltages will trigger the dc-link voltage protection or damage the lifetime of the capacitors.
To validate the above analysis, the mathematical model for unbalanced split-capacitor voltages is derived in this thesis. The derived mathematical model can accurately predict the waveforms and values of the capacitor voltages. The mathematical model will first be established under the circuit topology of single-phase half-bridge (SPHB) inverter, which is the basic structure of 3P4W inverter. After that, the equations can be extended to 3P4W topology and the mathematical model for 3P4W inverter can be derived. Details of the mechanism and the mathematical derivations are presented. Moreover, circuit-level computer simulations as well as hardware experimental results of a 3kVA prototype circuit are shown to verify the accuracy of the derived mathematical model.

並列關鍵字

mathematical model ； 3P4W grid-tied inverters ； split-capacitor voltages ； ADC signal deviation

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