三階多位元切換電流式三角積分調變器之設計與實現

本論文首先使用TSMC 0.35µm 2P4M CMOS製程來實現電阻補償技術之能隙參考電路及參考電流，該電路係由多種具高正溫度係數的電阻、二級運算轉導放大器與簡化的啟動電路所組成。本論文所提出之能隙參考電路係利用雙極性電晶體的n-p-n與p-n-p接面的寄生電阻為補償電阻，藉以產生與溫度無關之電壓和電流參考電路。當電源供應電壓為3.3 V時，該電路所量測到的參考電流為735.6奈安培(nA)，且參考電壓為888.1毫伏特(mV)，得到的功率消耗為91.28微瓦特(µW)。此外，量得的電壓溫度係數在溫度0oC ~100oC與30oC ~100oC分別為49 ppm/oC和12.8 ppm/oC，而其電流溫度係數在溫度0oC ~100oC則為119.2 ppm/oC；再者，該帶差參考電路在溫度大於30oC時可以產生穩定的參考電壓，而在溫度小於70oC時可以產生穩定的參考電流。其次，本論文使用TSMC 0.18µm 1P6M CMOS製程來設計並實現二種調變器晶片，第一種晶片是具有類比式錯誤消除邏輯電路與數位式梳型濾波器的全差動三級(二加一階)串接切換電流式三角積分調變器；而第二種晶片是使用四位元切換電容式快閃類比數位轉換器與增加式資料加權平均器之三階多位元切換電流式三角積分調變器。在該二種晶片之中，本論文提出一個電流式記憶單元，其可利用回授電路來降低輸入阻抗，並可利用共模前饋電路來改善輸出共模位準的差動取樣保持電路，該電路主要用於組成三角積分調變器之離散積分器。二加一階三角積分調變器是將第一級量化器輸入端接到第二級，此方式不僅降低電路的複雜度，同時容易以切換電流技術來完成。在調變器中，最主要的誤差(e2)是由第二級的一位元量化器所產生，並且可以藉由類比式錯誤消除邏輯電路來消除這個誤差。此晶片量測結果顯示，在電源供應電壓為1.8伏特(V)且取樣頻率為10.24 MHz、超取樣率為128，且頻寬為40 kHz時可以得到訊號雜訊比為67.3 dB、有效位元數為10.9位元(bits)、動態範圍為69 dB以及功率消耗為12.3毫瓦特(mW)，且其晶片面積約為0.20 × 0.21毫米平方(mm2)。第二種晶片係使用TSMC 0.18µm 1P6M CMOS製程來設計並實現一個三階多位元切換電流式三角積分調變器，其利用四位元切換電容式快閃類比數位轉換器來提高解析度，並使用增加式資料加權平均器將數位類比轉換器(DAC)所產生的誤差移到信號頻寬外，並且做一階的雜訊頻移。晶片量測結果顯示，在電源供應電壓為1.8伏特(V)、取樣頻率為10.24 MHz、超取樣率為256且頻寬為20 kHz時，可以得到訊號雜訊比為60.87 dB、有效位元數為9.82位元(bits)、動態範圍為60 dB以及功率消耗18.82毫瓦特(mW)，且其晶片核心面積為0.45 × 0.67毫米平方(mm2)。

關鍵字

切換電流式；三角積分調變器；增加式資料加權平均器

並列摘要

Firstly, this dissertation investigates a resistor-compensation technique for CMOS bandgap and current reference, which utilizes various high positive temperature coefficient (TC) resistors, a two-stage operational transconductance amplifier (OTA) and a simplified start-up circuit in 0.35-µm CMOS process. In the proposed bandgap and current reference, numerous compensated resistors, which have a high positive temperature coefficient (TC), are added to the parasitic n-p-n and p-n-p bipolar junction transistor devices, to generate a temperature-independent voltage reference and current reference. Because of the simplified start-up circuit, the proposed resistor-compensation bandgap and current reference can be started at 43 ns at a minimum supply voltage of 1.35 V. The measurements verify a current reference of 735.6 nA, the voltage reference of 888.1 mV, and the power consumption of 91.28 ?W at a supply voltage of 3.3 V. The voltage TC is 49 ppm/ oC in the temperature range from 0oC to 100oC and 12.8 ppm/ oC from 30oC to 100oC. The current TC is 119.2 ppm/ oC at temperatures of 0oC to 100oC. Measurement results demonstrate that when the temperature is above 30oC a stable voltage reference can be generated, while a constant current reference is generated at temperature below 70oC. Secondly, this dissertation presents the design and implementation of the switched-current delta-sigma modulator (DSM), which is fabricated using TSMC 0.18-μm CMOS technology. The fully differential third-order (2-1) switched-current (SI) cascaded delta-sigma modulator takes advantages of an analog error cancellation logic circuit and a digital decimation filter. Besides, a third-order multi-bit switched-current delta-sigma modulator with 4-bit SC flash analog-to-digital converter (ADC) and incremental data weighted averaging (IDWA) is considered, too. In those DSMs, the proposed differential sample-and-hold circuit performs with low input impedance due to feedback and width-length adjustment in SI feedback memory cell (FMC); and that a coupled differential replicate (CDR) common-mode feedforward circuit (CMFF) is used to compensate the error of the current mirror. Notice that the 2-1 architecture with only the quantizer input being fed into the second stage is introduced not only to reduce the circuit complexity, but also to be implemented easily is using the switched-current approach. Measurements reveal that the dominant error is the quantization error of the second one-bit quantizer (e2). This error can be eliminated using an analog error cancellation logic circuit. Measurements indicate that the signal-to-noise ratio (SNR), dynamic range (DR), effective number of bits (ENOB), power consumption and chip size are 67.3 dB, 69 dB, 10.9 bits, 12.3 mW, and 0.20 × 0.21 mm2, respectively, with a bandwidth of 40 kHz, a sampling rate of 10.24 MHz, an OSR of 128 and a supply voltage of 1.8 V. Finally, a third-order multi-bit switched-current delta-sigma modulator is designed with TSMC 0.18-µm 1P6M CMOS process. In the modulator, the 4-bit SC flash ADC improves resolution and IDWA are employed. In order to reduce the digital-to-analog converter (DAC) nonlinearity, the incremental data weighted averaging can achieve first-order DAC noise shaping moving the noise out of the signal band. Also, measurements indicate that the signal-to-noise ratio, dynamic range, effective number of bits, power consumption and chip size are 60.87 dB, 60 dB, 9.82 bits, 18.82 mW, and 0.45 × 0.67 mm2 (without I/O pad), respectively, with a bandwidth of 20 kHz (signal bandwidth 5 kHz ~ 25 kHz), a sampling rate of 10.24 MHz, an OSR of 256 and a supply voltage of 1.8 V.

並列關鍵字

switched-current ； delta-sigma modulator ； incremental data weighted averaging

參考文獻

1. X. Guan, A. Wang, A. Ishikawa, S. Tamura, Z. Wang and C. Zhang, “A 3V 110?W 3.1ppm/ oC curvature-compensated CMOS bandgap reference,” IEEE Int. Symp. Circuits Sys., Island of Kos, Greece, 2006, pp. 2861-2864.

2. K. N. Leung, P. K. T. Mok and C.Y. Leung, “A 2-V 23-?A 5.3-ppm/oC curvature-compensated CMOS bandgap voltage reference,” IEEE J. of Solid-State Circuits, vol. 38, no. 3, 2003, pp. 561-564.

4. P. Malcovati, F. Maloberti, C. Fiocchi, and M. Pruzzi “Curvature-compensated BiCMOS bandgap with 1-V supply voltage,” IEEE J. of Solid-State Circuits, vo1. 36, no. 7, 2001, pp. l076-1081.

5. J. Chen and B. Shi, “1 V CMOS current reference with 50 ppm/oC temperature coefficient,” Electronics Letters, vol. 39, no. 2, 2003, pp.209-210.

6. D.-O. Han, J.-H. Kim and N.-H. Kim, “Design of bandgap reference and current reference generator with low supply voltage,” 9th International Conference on Solid-State and Integrated-Circuit Technology, Beijing, 2008, pp. 1733–1736.

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三階多位元切換電流式三角積分調變器之設計與實現

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