切換電流式三角積分類比數位轉換器之設計

On the Design of a Switched-Current Delta-Sigma ADC

張國煊(Kuo-Hsuan Chang)

指導教授 ： 宋國明

國立臺北科技大學/機電學院/機電整合研究所/碩士(2005年)

https://doi.org/10.6841/NTUT.2005.00329

摘要

本論文主要是在研究切換電流式三角積分類比數位轉換器的設計，可將其分為類比的三角積分調變器以及數位的降頻數位濾波器兩部分個別討論。
類比部分探討的內容包含系統穩定度的設計與相關積體電路之非理想效應的成因和補償等，實際的硬體電路則是以切換電流式的技術為基礎，提出一個利用回授電路降低輸入阻抗以及共模前饋電路改善輸出共模位準的電流取樣電路，並以此設計出離散積分器以應用在三角積分調變器中。
在數位方面探討的是降頻數位濾波器的演算法設計，包含了梳型濾波器以及有限脈衝響應濾波器。針對簡化濾波器的演算法及以追求在相同演算法下減少電晶體數為目的，利用動態邏輯閘取代靜態邏輯閘的方式，減少晶片面積而降低成本的付出。
另外，在系統電路的實現上，採用了TSMC 0.35μm的互補式金氧半導體製程參數進行模擬，利用全客戶的設計流程方式，分別成功地設計出了(1)二階一位元和(2)三階三位元之三角積分調變器，以及(3)一個降頻率為16之梳型濾波器。

關鍵字

三角積分調變器 ； 電流取樣電路 ； 梳型濾波器

並列摘要

In this thesis, the major study is the design of a switched-current Analog-to-Digital Converter. Both the delta-sigma modulator (the analog part) and the decimator (the digital part) will be discussed separately.
Not only the system stability but also the compensation techniques of non-ideal effect in VLSI are considered. A current-mode sample-and-hold circuit is proposed. It consists of a feedback circuit to reduce the impedance at the input and a common mode feed-forward circuit to improve the common mode offset error at the output. The proposed circuit is used to create an integrator for the application of the delta-sigma modulator.
In the digital part, the algorithm of the decimator is discussed including the comb filter and the finite impulse response filter. In order to simplify the algorithm and reduce the number of MOSFETS used, the dynamic logic is used to replace the static logic for reducing the chip size and the cost.
Finally, the circuits are simulated with TSMC 0.35um CMOS process technology. By following the Full-Custom design flow, a second order 1-bit delta-sigma modulator, a third order 3-bits delta-sigma modulator, and a comb filter (decimation ratio is 16) are implemented successfully.

並列關鍵字

delta-sigma modulator, ； current-mode sample-and-hold ； decimator

參考文獻

[1] D. L. Fried, “Analog Sample-Data Filters,” IEEE J. Solid-State Circuits, Vol. SC-7, pp. 302-304, Aug. 1972.

[2] J. B. Hughes, N. C. Bird, and Lan C. Macbeth, “Switched Current – A New Technique for Analog Sample-Data Signal Processing,” IEEE Internatinal Symposium on Circuits and Systems, pp. 1154-1187, 1989.

[3] H. C Yang, T. S. Fiez, D. J. Allstot, “Current-Feedthrough Effects and Cancellation Techniques in Switched-Current Circuits”, Proc. Of Int. Symp. Circuits And Systems (ISCAS), pp. 3186-3188, May 1990, New Orleans, IEEE.

[4] T. S. Fiez, D. J. Allstot, G. Liang, and P. Lao, “Signal-Dependent Clock-Feedthrough Cancellation in Switched-Current Systems”, Proc. Of China 1991 Int. Conf. Circuits And Systems, Shenzhen, China, pp. 785-788, June 1991, IEEE.

[5] M. Song, Y. Lee, and W. Kim, “A Clock Feedthrough Reduction Circuit for Switched-Current Systems”, IEEE J. Solid-State Circ., Vol. 28, No. 2, Feb. 1993, pp. 133-137.