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  • 學位論文

二加一階多位元切換電流式三角積分調變器設計與實作

Design and Implementation of 2+1 Order Switched-Current Delta-Sigma Modulator with 3-bit Quantizer

指導教授 : 宋國明
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摘要


本論文旨在研究一個應用於語音系統之三角積分調變器,該調變技術對類比電路的非理想特性並不敏感,非常適合用來實現高解析度、高精準度的類比數位轉換器。提升系統階數一直是三角積分調變器提高解析度的方法。在單一迴路(single loop)和多路徑迴路(Interpolative)的高階系統中,系統的穩定度通常是設計者的一大隱憂,因此透過低階的系統來實現多級串接(MASH),以達到相對穩定的高階架構。此外,透過多階量化器來達成高解析度,並藉由資料權重平均演算法(DWA)來改善數位類比轉換器的非線性效應,降低其對系統的影響。 在電路系統的實現上,採用TSMC 0.18 μm的互補式金氧半導體製程參數來設計與模擬。模擬結果顯示,二加一階三位元多級串接架構,在取樣頻率為5.12百萬赫(MHz)與超取樣率(OSR)為128的條件下,其有效訊號頻寬為20仟赫(kHz),且其訊號雜訊失真比可達110分貝(dB),相當於有效位元數(ENOB)約18.04位元;而晶片於1.8V的供應電壓下,其消耗功率約為21.4mW,電路的工作電流範圍為-5μA~+5μA。

並列摘要


A sigma-delta modulator (SDM) is proposed in this thesis for audio system.SDM is well suitable for the realization of a high-resolution,high-accuracy and narrow-band analog-to-digital converter (ADC) because this modulator is insensitive to the imperfections on analog components.The higher the order is,the higher the resolution is for SDM. There are several types of high-order SDM, such as single-loop archiecture, interpolative archiecture and multi-stage noise shaped (MASH) archiecture.The stability is serious problem for single-loop and interpolative architecture. MASH is a cascade architecture of low-order stages.That is, the whole MASH archiecture walks stable. Besides, the multi-bit quantizer to is used accomplish high resolution, and that the nonlinear error of DAC can be improved with data weighted averaging (DWA) logic. The systematic simulation was completed with TSMC 0.18 μm CMOS process. The simulation results show that the sampling rate is 5.12 MHz, the oversampling ratio is 128, and the signal bandwidth is 20 kHz for audio system. Moreover the signal-to-noise and distortion ratio(SNDR),the effective number of bit (ENOB),and the power consumption are 110 dB,18.04 bits,and 21.4 mW,respectively,with the supply voltage of 1.8V.and with input current range of -5 μA~+5 μA.

參考文獻


[28] 侯岳宏,切換電流式三角積分調變器設計與實作,碩士論文,國立台北科技大學電機工程系,台北,2008。
[1] R. J. Baker, CMOS Mixed-Signal Circuit Design ,SECOND EDITION, IEEE, 2002.
[2] D. A. Johns and K. Martin, Analog Integrated Circuit Design, John Wiley & Sons, 1997.
[4] T. L. Brooks, D. H. Robertson, D. F. Kelly, A. D. Muro, and S. W. Harston, ”A cascaded sigma-delta pipeline A/D converter with 1.25 M Hz signal bandwidth and 89dB SNR,” IEEE Journal of Solid-State Circuits, vol. 32, no. 12,pp.1896-1906, Dec. 1997.
[5] Y. Geerts and M. Steyaert and W. Sansen, Design of Multi-Bit Delta-Sigma A/D Converters, Boston, Klower Academic Publishers, 2002.

被引用紀錄


李念祖(2013)。具數位消除電路之四級MASH切換電流式三角積分調變器〔碩士論文,國立臺北科技大學〕。華藝線上圖書館。https://www.airitilibrary.com/Article/Detail?DocID=U0006-2106201315314500
顧政宗(2013)。具有電源切換功能之低功率四階切換電容式三角積分調變器〔碩士論文,國立臺北科技大學〕。華藝線上圖書館。https://www.airitilibrary.com/Article/Detail?DocID=U0006-1507201311090200

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