切換電流式三角積分調變器設計與實作

Design and Implementation of Switched-Current Delta-Sigma Modulator

侯岳宏(Yueh-Hung Hou)

指導教授 ： 宋國明

國立臺北科技大學/電資學院/電機工程系研究所/碩士(2008年)

https://doi.org/10.6841/NTUT.2008.00012

摘要

本論文主要是在研究切換電流式三角積分類比數位轉換器的設計，製作二加ㄧ階多級串接三角積分調變器。探討的內容包含系統穩定度的設計與相關積體電路之非理想效應的成因和補償等，實際的硬體電路則是以切換電流式的技術為基礎，提出一個利用回授電路降低輸入阻抗以及共模前饋電路改善輸出共模位準的電流取樣電路，並以此設計出離散積分器以應用在三角積分調變器中。
三角積分調變技術不但可以達到較高的精準度，而且對其內部組成電路的要求不像其他類比數位轉換器這樣嚴苛，它在高精準度類比數位轉換器的實現上提供了許多卓越的優點。正因為三角積分調變技術對類比電路的表現要求不高，所以就功率的消耗上也可大幅的減少，另外相較於其他種類的類比數位轉換器，其電晶體的數量和電路的複雜度也簡單得多。同時三角積分調變器也容許將主要的電路性能和功率消耗集中在其輸入級的類比電路中。
整篇論文簡單的描述了三角積分調變器基本原理，以及三角積分調變器從設計到電路實現。在系統電路的實現上，我們採用TSMC 0.18μm的互補式金氧半導體製程參數來設計與模擬，模擬結果顯示，該二加一階一位元多級串接架構，在取樣頻率為10.24MHz與超取樣率為128的條件下，其有效應頻寬為40仟赫，且其SNR可達83dB，相當於有效位元數約13.5位元。

關鍵字

三角積分調變器 ； 二加一階三角積分調變器 ； 切換電流電路 ； 共模前饋電路。

並列摘要

In this thesis, the major study is focused on the design of a switched-current analog-to-digital converter which composes of a two-plus-one multistage sigma-delta modulator. Not only the system stability but also the compensation techniques of non-ideal effect in VLSI are considered. A current-mode sample-and-hold circuit is proposed. It consists of a feedback circuit to reduce the output impedance and a common-mode feed-forward circuit to improve the common mode offset error at the output. The proposed circuit is used to create an integrator for the application of the delta-sigma modulator.
Utilizing the sigma delta modulator not only can reach better accuracy, but also can make up the request of the circuit to without any tight and severe efforts. There are some advantages in the realization of the high accuracy sigma delta modulator, including the small area of the analog circuit, low power consumption and simple CMOS circuit.
In this thesis, the basic principle of sigma-delta modulator and the design flow chart from simulation to implement will be presented with great attention. In the implementation of the circuit ,the library of TSMC 0.18μm CMOS process is ultilized.The simulated results show that the sampling rate is 10.24 MHz, the oversampling ration is 128, the bandwidth is 40 kHz , and the maximum signal to noise and distortion ratio (SNDR) is 83 dB, respectively.

並列關鍵字

delta-sigma modulator ； two-plus-one multistage sigma-delta modulator ； switched-current circuit ； common-mode feedforward (CMFF).

參考文獻

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