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  • 學位論文

四階MASH切換電流式三角積分調變器設計與實作

Design and Implementation of Four-Order MASH Switched-Current Delta-Sigma Modulator

指導教授 : 宋國明
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摘要


本論文研究切換電流式記憶元件應用於三角積分類比數位轉換器的設計,並藉由製作四階MASH多級串接三角積分調變器來探討系統穩定度與相關積體電路之非理想效應的成因,進而來找出切換電流式記憶元件擁有的優點及適合應用的方向。   本論文描述三角積分調變器基本原理,以及三角積分調變器從系統行為模式到電路實現。系統架構方面,本篇論文採用了二加二階多級串階式,電路實現則是採用切換電流式技術。在系統電路的實現上,採用TSMC 0.18μm的互補式金氧半導體製程參數來設計與模擬。模擬結果顯示,該四階MASH一位元多級串接架構,在取樣頻率為5.12百萬赫與超取樣率為128的條件下,其有效頻寬為20仟赫,且其訊號雜訊比可達85分貝,相當於有效位元數約13.8位元。   最後,藉由四階MASH一位元多級串接架構實作的經驗發現,切換電流式電路有其低供應電壓的特性,並修改原有的切換電流式電路,實現了一低電壓供應的切換電流式三角積分調變器。

並列摘要


This thesis investgates a switched-current memory cell which is used in the high-order delta-sigma modulator. The purpose is to certinify the advantage of switched-current memory cell with the design of four order MASH delta-sigma modulator. Furthermore, both the system stability and the factor of non-ideal effect are discussed in the proposed delta-sigma modulator. In this thesis, the basic theory and accomplishment of the process of system behavior to circuit implementation of delta-sigma modulator are described. In system structure a four order MASH delta-sigma modulator which is designed with switched-current is presented. In chip implement, the TSMC 0.18μm CMOS process is used to design and simulate the propose switched-current delta-sigma modulator. As show in the simulation result, the signal-to-noise ratio is 85dB, which is roughly equal to 13.8 bit, at the sampling frequency of 5.12MHz, the oversampling ratio of 128 and the signal bandwidth og 20KHz. Notify that a more interesting topic is explored with switch-current technique in design a four order MASH delta-sigma modulator. The tranditional switch-current technique is modified to establish a new low voltage delta-sigma modulator based on the interesting switch-current technique.

參考文獻


[37] 侯岳宏,切換電流式三角積分調變器設計與實作,碩士論文,國立台北科技大學電機工程系,台北,2008。
[1] R. Jacob Baker, CMOS: Mixed-Signal Circuit Design SECOND EDITION, IEEE, 2002.
[2] D. A. Johns and K. Martin, Analog Integrated Circuit Design, John Wiley & Sons, 1997.
[4] Todd L. Brooks, David H. Robertson, Daniel F. Kelly, Anthony Del Muro, and Stephen W. Harston, ”A Cascaded Sigma-Delta Pipeline A/D Converter with 1.25 M Hz Signal Bandwidth and 89dB SNR,” IEEE Journal of Solid-State Circuits, Vol. 32, No. 12, Dec. 1997.
[5] Yves Geerts and Michiel Steyaert and Willy Sansen, Design of Multi-Bit Delta-Sigma A/D Converters, Boston, Klower Academic Publishers, 2002.

被引用紀錄


陳世昕(2012)。二加一階多位元切換電流式三角積分調變器設計與實作〔碩士論文,國立臺北科技大學〕。華藝線上圖書館。https://www.airitilibrary.com/Article/Detail?DocID=U0006-1607201210573100
李念祖(2013)。具數位消除電路之四級MASH切換電流式三角積分調變器〔碩士論文,國立臺北科技大學〕。華藝線上圖書館。https://www.airitilibrary.com/Article/Detail?DocID=U0006-2106201315314500
顧政宗(2013)。具有電源切換功能之低功率四階切換電容式三角積分調變器〔碩士論文,國立臺北科技大學〕。華藝線上圖書館。https://www.airitilibrary.com/Article/Detail?DocID=U0006-1507201311090200

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