本論文主要是研究運用於語音系統之低功率消耗三角積分調變器,其採用超取樣與雜訊頻移技術,該項技術對類比電路的非理想特性並不敏感,因此非常適合用來實現高解析度、高精準度的類比數位轉換器。再者,如何使三角積分調變器同時具有高效能及低功率消耗更是今後的研究趨勢。一般而言,運用在三角積分調變器中之運算放大器,其狀態在取樣模式及積分模式時皆為開啟,因而消耗了三角積分調變器整體的大部分功率。據此,本論文設計一個切換電源式運算放大器,當狀態為取樣模式時,令其關閉;而在積分模式時,令其開啟。如此可以減少該運算放大器在取樣模式時的功率消耗,達到省電效果。 在電路系統的實現上,本論文採用TSMC 0.18μm的互補式金氧半導體製程參數來設計電路與模擬。在取樣頻率為5.12 MHz、超取樣率(OSR)為128且有效頻寬為20kHz的條件下,模擬結果顯示該調變器之信號對雜訊與失真比(SNDR)可達91.14分貝(dB),相當於有效位元數(ENOB)為14.85位元;且在1.8伏特電源供應下,整體功率消耗約為647μW。
A low power delta-sigma modulator(DSM) is proposed in this thesis for audio system. Oversampling-rate technique and noise-shaping technique are used to implement the proposed DSM. Those techniques are well suitable for developing the analog-to-digital converter(ADC) with high-resolution and high-accuracy, because they are insensitive to the imperfections on analog components. Especially a DSM must operate with high-resolution, high-accuracy and low power consumption. To meet this demand, a operational amplifier with switched power supply is proposed. It will turn on in integrating–mode and turn off in sampling-mode. With the switched technique, the DSM reduces the power consumption considerately. The simulation results of Four-Order Switched-Capacitor DSM, which is implemented with TSMC 0.18μm CMOS technology, show that the signal-to-noise and distortion ratio(SNDR), the effective number of bit(ENOB), and the power consumption are 91.14 dB, 14.85 bits, and 647 μW, respectively, with the supply voltage of 1.8V at the sampling rate is 5.12 MHz, the oversampling ratio is 128, and the signal bandwidth is 20 kHz.