應用於電容感測之高能效三角積分時間數位轉換器

Energy Efficient Delta-Sigma Time-to-Digital Converters for Capacitive Sensing Applications

鄭楷翰(Kai-Han Cheng)

指導教授 ： 呂良鴻

國立臺灣大學/電機資訊學院/電子工程學研究所/碩士(2018年)

https://doi.org/10.6342/NTU201804135

摘要

近年來，隨著互補式金屬氧化物半導體製程的不斷演進，下降的操作電壓使得類比電路的設計面臨更大的挑戰。從而，將訊號在時域上進行操作提供了一個可能的方向去解決問題。因此本論文使用了數種時域訊號處理的技巧，使用90奈米互補式金氧半製程來實做高能源效率的三角積分資料轉換器。首先，此研究透過免閘式環型震盪器來實現一個二階三角積分時間至數位轉換器，操作在 1.0 伏特的情況下，晶片功耗為 330 微瓦，並且在1 MHz的頻寬內有 11.3 位元的解析度，達到 0.25 pJ/c.-s. 的品質因數。進一步的，透過一個高線性度的電容至時間轉換電路來將時間至數位轉換器應用至電容感測介面電路，操作在 0.6 伏特的情況下，晶片功耗為 6.77 微瓦，此電路的輸入電容範圍為8皮法拉，並且在2 kHz的頻寬內有 11.2 位元的解析度，達到0.72 pJ/c.-s.的品質因數。

關鍵字

三角積分 ； 時間數位轉換器 ； 介面電路 ； 電容數位轉換器

並列摘要

In recent years, as CMOS technology continues to advance, design of traditional analog circuits becomes more challenging due to the lower operation voltage. Thus, operating signals in time-domain paves a possible way to alleviate the problem. This thesis utilizes several time-mode signal processing techniques for energy efficient delta-sigma data converters. Fabricated in a 90-nm CMOS process, a second-order delta-sigma time-to-digital converter (TDC) which consumes 330 μW from a 1.0-V supply is realized with gated-free ring oscillators. This design demonstrates a resolution of 11.3 bits within 1-MHz signal bandwidth and achieves an FoM of 0.25 pJ/c.-s. Furthermore, a capacitance-to-digital converter (CDC) composed of a highly linear capacitance-to-time circuit and the proposed TDC is implemented. Consuming 6.77 μW from a 0.6-V supply, the CDC demonstrates a resolution of 11.2 bits in 2-kHz signal bandwidth. This design achieves an FoM of 0.72 pJ/c.-s. for an input capacitance range of 8 pF.

並列關鍵字

delta sigma ； TDC ； sensor interface ； CDC

參考文獻

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