全管線覆蓋的自我測試程式樣板開發

Development of Self-Test Program Template with Full Pipeline Coverage

李其哲(Chi-Jhe Li)

指導教授 ： 黃俊郎

國立臺灣大學/電機資訊學院/電子工程學研究所/碩士(2022年)

https://doi.org/10.6342/NTU202203404

摘要

由於汽車電子和醫療電子產品的快速發展帶來的系統可靠性問題，軟體自我測試（Software-based self-test, SBST）受到更多關注。

在之前的研究[1]中，提出了一種基於模組無關的（module-independent）測試程式樣板（template）和受約束的自動測試型樣產生系統（constrained automatic test pattern generation）的轉換方法，將全掃描測試型樣（full-scan test pattern）轉換為測試程式。本文在前人研究的基礎上提出了一系列改進方法。首先也是最重要的，我們提出了一種增強型測試程式樣板及與其對應的將測試型樣轉換為測試程式的轉換方法。該樣板可以有效提高型樣到程式轉換過程的轉換精度，從而提高測試程式的故障覆蓋率（fault coverage）。此外，我們改進了自動測試型樣產生系統的約束方法，讓只能適用於具有固定（fix-length）長度指令集架構（instruction set architecture）的處理器的測試程式生成方法也可以擴展到具有可變長度（variable-length）指令集架構的處理器。最後，我們在生成測試程式的流程中加入了程式段篩選（segment filtering）機制，有效減少了生成的測試程式大小。

所提出的技術在RV32IC處理器上得到驗證，在493KB的程式大小下實現了 91.23%的轉態延遲故障（transition delay fault, TDF）覆蓋率。與之前的研究[2]相比，此技術實現了6.65%的故障覆蓋率提高和78%的程式大小減少。

關鍵字

軟體自我測試 ； 轉態延遲故障 ； 功能約束 ； 測試樣板 ； RV32IC

並列摘要

Software-based self-test (SBST) has attracted more attention due to system reliability concerns derived from the rapid development of automotive electronics and medical electronic products.

In a previous research [1], a conversion methodology based on module-independent template and constrained automatic test pattern generation (ATPG) to convert full-scan test patterns into test programs was proposed. This paper proposes a series of improved methods based on the previous work. First and foremost, we propose an enhanced template and its corresponding pattern-to-program conversion method. This template can effectively improve the conversion accuracy of the pattern-to-program conversion process, thereby improving the fault coverage (FC) of the test program. Besides, we improved the ATPG constraint method so that the test program generation method that can only be applied to processors with fix-length instruction set architecture (ISA) can also be extended to processors with variable-length instruction set architecture. Last but not least, we added a segment filtering mechanism to the program generation flow to effectively reduce the size of the generated test program.

The proposed technique is validated on a RV32IC processor and achieves 91.23% transition delay fault (TDF) coverage with a program size of 493KB. Compared with the previous research [2], this technique achieved 6.65% fault coverage improvement and 78% program size reduction.

並列關鍵字

Software-Based Self-Test ； Transition Delay Fault ； Functional Constraint ； Test Template ； RV32IC

參考文獻

K.-H. Chen, B.-Y. Yang, J.-R. Liang, H.-L. Chen, and J.-L. Huang, “Automatic test program generation for transition delay faults in pipelined processors,” in 2021 IEEE International Test Conference in Asia (ITC-Asia), pp. 1–6, 2021.

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M. Psarakis, D. Gizopoulos, E. Sanchez, and M. Sonza Reorda, “Microprocessor software-based self-testing,” IEEE Design Test of Computers, vol. 27, no. 3, pp. 4–19, 2010.

K. Kambe, M. Inoue, and H. Fujiwara, “Efficient template generation for instructionbased self-test of processor cores,” in 13th Asian Test Symposium, pp. 152–157, 2004.