液晶顯示器源極驅動器晶片上升時間以及下降時間測試的可測試性設計

本篇論文提出了一個薄膜電晶體液晶顯示器源極驅動器晶片的可測試性設計，此可測試性設計可以量測輸出頻道的上升下降時間以及電壓偏差。所提出的可測試性設計在晶片上輸出頻道同時做電壓的比較，如此一來可大量減少測試機台所需要的輸入輸出針腳。根據模擬的結果可知，電壓偏差測試的準確度為2mV，上升下降時間測試的準確度為100ns。所提出的技術節省了數百個輸入輸出針腳，以及降低了百分之四十的測試時間。雖然增加了百分之十的面積成本，但可測試性設計建構在切割線上，並不會對原先的設計有所影響。源極驅動器晶片以及可測試性設計均以0.18μm的製程技術設計並且完成。

關鍵字

可測試性設計；源極驅動器晶片；上升時間；下降時間

並列摘要

This thesis presents a DFT technique to measure the rise/fall time and the offset of TFT-LCD source driver IC. The proposed DFT performs on-chip voltage comparison in parallel so the required number of tester channels is greatly reduced. According to simulation results, the accuracy of offset testing is 2mV and the rise/fall tine testing is 100ns. The proposed technique saves hundreds of I/O pins and reduces the total test time by 40%. Although the area penalty is 10%, the DFT circuitry is implemented on the scribe line so it is non-intrusive to the original design. The DFT has been implemented on an industrial design in 0.18μm technology.

並列關鍵字

DfT ； Source driver ； rise time ； fall time

參考文獻

[Al-Rawi 00] Chazi Al-Rawi, “A New Dynamic Latch Offset Measurement Technique For Offset Cancellation,” Circuit System Signal Processing, VOL.21, NO.2, pp.137-148, 2002.

[Banihashemi 01] Mehdi Banihashemi et al., “A Low-Power, High-Resolution, 6Mhz Comparator,” European Conference on Circuit Theory and Design, VOL.3, pp.329-332, AUGUST 2001.

[Banihashemi 04] Mehdi Banihashemi, “A High-Speed High-Resolution Comparator,” IEEE International Midwest Symposium on Circuit and Systems, VOL.1, pp.81-84, 2004.

[Lin 04] San L. Lin and Samiha Mourad, “On-Chip Rise Time Measurement,” IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT, VOL.53, NO.6, pp.1510-1516, DECEMBER 2004.

[Lu 08] Chih-Wen Lu and Lung-Chien Huang “A 10-Bit LCD Column Driver With Piecewise Linear Digital-to-Analog Converters,” IEEE Journal of Solid-State Circuit, VOL.43, NO.2, pp.371-378, FEBRUARY 2008.

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液晶顯示器源極驅動器晶片上升時間以及下降時間測試的可測試性設計

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