平面顯示器源極驅動器晶片可測試性設計技術

A Design-for-Test Technique for Flat Panel Display Source Driver ICs

林士軒(Shih-Hsuan Lin)

指導教授 ： 黃俊郎

國立臺灣大學/電機資訊學院/電機工程學研究所/碩士(2012年)

https://doi.org/10.6342/NTU.2012.10594

摘要

測試平面顯示器源極驅動器晶片是在生產晶片中一個高成本的步驟。需要大量的類比量測和大量測試點是造成高成本最主要的原因。

在這篇論文中，我們提出一個方法去測試源極驅動器晶片，而這個方法可以讓我們在較短的時間內完成測試。我們對測試一個有著1,000通道和8位元精準度的數位類比轉換器的短路和斷路做為目標，運用在電源供應器觀察電流的方式去對它做測試。為了增加我們可以測到的範圍，我們加了兩種可測試性設計技術；參照多工器和回流多工器。參照多工器是用來增加在正常電路和異常電路的電流的差異，如此一來我們可以增進我們的測試精準度。而回流多工器是用來建造一個用來測試斷路的回流電流。此外，我們提出一個輪轉測試資料的方法來增加測試平行度。因為平行測試我們降低了更大量的類比量測次數。而我們最後會使用HSPICE的模擬來驗證這個方法的正確性跟有效性。

關鍵字

平面 ； 顯示器 ； 源極驅動器 ； 晶片 ； 可測試性 ； 設計技術

並列摘要

Testing flat panel display source driver ICs is a costly process in manufacture; the root cause is the huge amount of analog measurements and analog access points required to test the internal DAC (digital-to-analog) array.

In this thesis, a scheme for testing source driver ICs is presented with a great gain in time efficiency. We test the open and short defects in a 1,000-channel 8-bit DAC by measuring the current from Gamma voltage source pins. To improve the fault coverage, two DfT techniques are proposed: REF-multiplexer (Reference multiplexer) and FB-multiplexer (Flow back multiplexer). REF-multiplexers enlarge the current deviation from faulty circuit to fault free one, thus we can improve the test accuracy. FB-multiplexer establishes the flow-back current to test open fault. Moreover, rotating pattern scheme is proposed to improve the test parallelism. By concurrent testing, we can test multiple channels in parallel and thus reduce great amount of analog measurement. The validity and the effectiveness of the proposed method are verified by HSPICE simulation.

並列關鍵字

Design-for-Test ； Technique ； Flat Panel Display ； Source Driver ； ICs

參考文獻

[1] M. Hashizume, T. Nishida, H. Yotsuyanagi, T. Tamesada, and Y. Miuram, “Testable Design of Resistor String DACs,” in Electronic Design, Test and Applications, 2006.

[2] M. Hashizume, Y. Hata, T. Nishida, H. Yotsuyanagi, and Y. MiuraCurrent, “Testable Design of Resistor String DACs,” in Asian Test Symposium, 2007, pp.399-403.

[3] K. Arabi, K. Kaminska, and M. Sawan, “On chip testing data converters using static parameters,” IEEE Transactions on VLSI Systems, vol. 6, no. 3, pp. 409–419, 1998.

[4] Y. Wen and K. Lee, “BIST structure for DAC testing,” IEEE Electronics Letters, vol. 34, no. 12, pp. 1173–1174, 1998.

[5] J.-L. Huang, C.-K. Ong, and K.-T. Cheng, “A BIST scheme for on-chip ADC and DAC testing,” in Design, Automation & Test in Europe, 2000, pp. 216–220.