薄膜電晶體液晶顯示器源極驅動IC之輸出偏移電壓可測試設計

A DFT Technique for Output Offset Voltage Testing of TFT-LCD Source Driver IC

陳佳韶(Chia-Shao Chen)

指導教授 ： 李建模

國立臺灣大學/電機資訊學院/電子工程學研究所/碩士(2008年)

https://doi.org/10.6342/NTU.2008.00094

摘要

本論文提出一薄膜電晶體液晶顯示器源級驅動IC之輸出偏移電壓可測試設計。此設計可平行執行晶片上之電壓比較，故測試機台所需之頻道數可大幅度降低。模擬結果顯示輸出偏移電壓量測之最高準確度為0.371mV，此設計可節省上百組I/O腳位與51%之測試時間。可測試設計電路實作於晶片之切割道上，故其對原IC為非侵入式設計，此電路佈局不需耗用任何額外的晶圓面積。

關鍵字

可測試設計 ； 偏移電壓 ； 測試 ； 薄膜電晶體液晶顯示器 ； 源極驅動晶片

並列摘要

This thesis presents a DFT technique to measure the output offset voltages of TFT-LCD source driver IC. The proposed DFT performs on-chip voltage comparison in parallel so the required number of tester channels is greatly reduced. According to simulation results, the accuracy of output offset voltage measurement is 0.371mV. The proposed technique saves hundreds of I/O pins and reduces the total test time by 51%. The DFT circuitry is implemented on the scribe line so it is non-intrusive to the original design. This DFT layout results in zero area overhead.

並列關鍵字

DFT ； offset voltage ； testing ； TFT-LCD ； source driver

參考文獻

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