薄膜電晶體液晶顯示器源極驅動晶片之研究

Study of TFT-LCD Source Driver ICs

蕭敬民(Ching-Min Hsiao)

指導教授 ： 林佑昇

共同指導教授 ： 盧志文

國立暨南國際大學/科技學院/電機工程學系/博士(2012年)

摘要

為了提高畫面品質，必須採用高解析度和高色深的源極驅動器積體電路(IC)。要達到更高的解析度，源極驅動器必須提供更多的輸出通道。要增加色深，DAC的位元數也必須增加，造成DAC的面積增加。因為源極驅動器的每個輸出通道需要一個DAC，因此源極驅動器通常包含數百個DAC，這佔據了大部分的晶片面積。因此市場上對於高解析度，高色深但低成本的源極驅動器IC有很大的需求。本研究提出三種省面積的DAC，給不同應用的液晶顯示的源極驅動器使用。
對於小尺寸面板的液晶顯示器應用。吾人提出類管線式DAC技術來實現高資料轉換速率的九位元源極驅動器IC。為了減少電荷注入誤差，DAC使用拔靴帶式開關。以0.35-μm CMOS製程實作一個30通道的源極驅動器來驗證所提出的類管線式DAC。量測到最差的DNL和INL分別是0.25LSB和0.33LSB。平均每通道的資料轉換時間是16 ns。品質因素(FoM)是0.2 pJ/bit-mm2 ，比目前技術小3到39倍。量測結果驗證，所提出的九位元類管線式DAC，非常適合應用在小尺寸的液晶顯示源極驅動器IC。
對於中尺寸面板的液晶顯示器應用。吾人提出一個使用電壓內插技術的省面積十位元DAC，給液晶顯示源極驅動器IC使用。提出的DAC包含一個六位元的電阻式DAC和一個使用1.6位元電流式內插元件的嵌入式四位元DAC運算放大器。六位元電阻式DAC使用單電壓選擇器取代傳統的雙電壓選擇器，因此選擇器面積較小。又因為1.6位元電流式內插元件使用二位元權重的參考電壓，使得嵌入式四位元DAC運算放大器可以使用較少的差動對來完成電壓內插。所以晶片面積又可以進一步的縮小。雛型的十位元DAC以0.35-μm CMOS製程來實現，最差的DNL和INL為0.45和0.93LSB。提出的十位元DAC面積僅占傳統8位元電阻式DAC的64%。
對於大尺寸面板的液晶顯示器應用。吾人提出一個使用切換電容技術來達到電壓相加的十位元DAC。包含一個三位元電阻式DAC和一個有高驅動能力的切換電容式八電壓相加器。三位元電阻式DAC產生一個輸出電壓，以及三到九位元的數位值分別和其相應的二位元權重類比電壓值相乘，所產生的七個輸出電壓，經由切換電容式八電壓相加器相加，產生十位元輸出。雛型的十位元DAC使用0.35-μm CMOS製程實現，最差的DNL和INL為0.76和1.56LSB。DAC每個通道的晶片面積為35 μm × 410 μm，在同樣製程下，比目前技術的其他電路面積更小。取最終電壓0.2%誤差值，所量到的穩態時間只有5 μs，相較於目前的切換電容式DAC技術，時間更短。

關鍵字

數位類比轉換器 ； 液晶顯示器 ； 源極(行)驅動器 ； 管線 ； 數位類比轉換內嵌式運算放大器 ； 切換電容式數位類比轉換器 ； 電壓相加器

並列摘要

To improve the image quality of the display, high-resolution and high-color-depth source driver ICs are required. Achieving a higher resolution, more output channels of the source driver are needed. Extending color depth for the source driver requires high digital-to-analog converter’s (DAC’s) bit number, leading to an increase of DAC’s area. Since each output channel of the source driver needs one DAC, a source driver generally includes hundreds of DACs which occupy most silicon die size. Hence, there is a great demand for high-resolution, high-color-depth but low-cost source driver ICs. This study proposes three area-efficient DACs for LCD source driver ICs in different applications.
For the small-size LCD panel, a quasi-pipeline DAC is proposed to implement a 9-bit source driver IC with high conversion rate. To minimize the charge injection error, we also utilize bootstrapped switches in the proposed DAC. Using 0.35-μm CMOS technology, a 30-channel source driver with quasi-pipeline DACs is implemented to validate the proposed DAC’s performance. The maximum DNL and INL are measured as 0.25 LSB and 0.33 LSB, respectively. The averaged data conversion time is 16 ns per channel. The Figure of Merit (FoM) of the proposed DAC is 0.2 pJ/bit-mm2, which is smaller (by a factor of 3-39) than that of prior arts. The measured results indicate that the proposed 9-bit quasi-pipeline DAC is highly suitable for small-format 16-million-color LCD source driver ICs.
For the medium-size LCD application, we propose a 10-bit DAC with interpolation technique for compact LCD column driver ICs. The proposed DAC combines a 6-bit RDAC and a 4-bit DAC-embedded op with 1.6-bit current-mode interpolation cells. The 6-bit RDAC uses a one-voltage selector instead of a two-voltage selector; therefore, it requires a smaller silicon die area for the voltage selector than conventional ones. Fewer differential pairs are required for the voltage interpolation because the DAC-embedded op uses 1.6-bit interpolation cells with binary-weighted reference voltages. This reduces the silicon die area further. The 10-bit DAC prototype is realized in 0.35-μm CMOS technology with the worst DNL/INL of 0.45/0.93 LSB. The 10-bit DAC occupies only 64 % of the conventional 8-bit RDAC area.
For the large-size LCD application, a 10-bit switched-capacitor voltage-summing DAC is introduced. This 10-bit DAC consists of a 3-bit RDAC and an 8-voltage switched-capacitor summer with high driving capability. The switched-capacitor summer adds up the output voltage of the 3-bit RDAC and the products of the input digital bit value and the corresponding binary-weighted voltage from bits 3 to 9. The 10-bit DAC prototype is realized using 0.35-μm/0.5-μm CMOS technology, with the worst-case DNL/INL at 0.76/1.56 LSB. The die area per channel is 35 μm × 410 μm, which is more compact than state-of-the-art circuits implemented with the same technology. The settling time to reach 0.2% tolerance of the final voltage is only 5 μs, smaller than that of previous switched-capacitor (cyclic) DACs.

並列關鍵字

DAC ； LCD ； source (column) driver ； pipeline ； DAC-embedded op ； switched-capacitor DAC ； voltage summer

參考文獻

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