- 學位論文
超低電壓低漏電延遲緩衝器電路設計
Ultra Low Voltage And Low Leakage Delay Buffer Circuit Design
摘要
在這篇論文裡，我們提出了一種可以操作在超低電壓的延遲緩衝器，我們捨棄了常見由隨機存取記憶體(SRAM)組成的架構，而是根據我們所需要的功能，採用了環狀計數型態的緩衝器架構(ring counter based delay buffer)，我們以環狀計數器(ring counter)來當作位址指定器，來降低動態功率(dynamic power)的消耗，而資料儲存的部分，我們使用了10T的架構，這比傳統的6T架構的memory cell更適合工作在超低電壓(次臨界區域-sub-threshold region)，進而整個延遲緩衝器可以比傳統的設計更為省電。 為了降低動態功耗，我們在延遲緩衝器中的環狀計數器採用閘式時脈架構，我們充分的利用延遲緩衝器的特性，因此可以預先知道那些部份的電路沒有被使用到，那麼我們就會關閉當時沒有使用到的閘式時脈驅動器以及環狀計數器，來減少不必要的能量消耗。同樣的觀念也可以使用在輸入端與輸出端的驅動器，來降低整體的動態功率。 我們為了讓延遲緩衝器能夠工作在低電壓，因此我們使用的記憶晶胞(memory cell)是10顆電晶體的架構，我們把讀取跟寫入的路徑分開，以避免讀取時造成資料翻轉的錯誤。除此使用10T外，我們還使用了虛擬的電源跟虛擬的地(virtual VDD & virtual ground)來幫助記憶裝置的讀取跟寫入。除此之外，我們使用了穿插式的讀取資料線(interleaved read bit line)來避免讀取時間的變異(time variation)造成的讀取錯誤。而在資料輸入的與輸出的驅動器，我們修改了原本常見的三態反向器，根據他們的需求，各自更換了適合的電路，讓輸入端更快更省電，而輸出端在低電壓更為穩定。藉由上面提到的架構，我們完成了一個可以操作在0.2V的延遲緩衝器，比傳統1V的版本，耗電量可以降低了許多，其中漏電流更降低了約99%。
並列摘要
In this thesis, we propose a delay buffer which can be operated in ultra low voltage. Unlike the conventional structure which is SRAM based delay buffer. According to the function we need, we choose ring counter based delay buffer instead. We use ring counter as an address pointer. By this method, we can reduce the dynamic power. About memory cell part, we choose 10T memory cell. It is more suitable than conventional 6T memory cell in operating in subtheshold region. Therefore, the delay buffer can save a lot of power than conventional design. In order to reduce dynamic power consumption , we use gated clock structure in the ring counter. We adequately use the characteristic of delay buffer. We can know that which part will not be used in advanced. Therefore, we will disable the clock gated tree and part of ring counter that we don't use. It can reduce the redundant power consumption. Also, we can apply this idea to the input and output driver to reduce the dynamic power of delay buffer. In order to make delay buffer operate in ultra low voltage, so the memory cell type we use is 10T. We can separate the path we read and write. It can avoid the data flipping when we read the stored data. Besides 10T cell type, we also apply virtual VDD and virtual ground methods to help write data into the cell and read data from the cell. Besides, we use bitline interleaving structure to avoid read failure that caused by time variation. In input and output driver tree, we modify the conventional tristate inverter. According to the requirement, we replace them with a suitable version. In input driver tree, we make it faster and lower power. In the output driver, we can operate in even more stable in low voltage than conventional tristate inverter. By the method we mentioned above, we implement a delay buffer which can be operate in 0.2 voltage. Compare with conventional 1 voltage version, the power consumption is reduced, and the leakage power reduce about 99%.
並列關鍵字
delay buffer ； ring counter ； memory cell ； ultra low voltage ； subthreshold region ； low power ； low leakage參考文獻
延伸閱讀
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- 郭裔平（2014）。Ultra-Low Voltage All Digitally Controlled Linear Voltage Regulator Design for Event-Driven Energy-Efficiency Sensing Platform〔碩士論文，國立交通大學〕。華藝線上圖書館。https://doi.org/10.6842/NCTU.2014.00973
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