採用對稱性迴路之閘式壓控震盪器突發式時脈資料回復電路

A Burst-Mode CDR Using a GVCO with Symmetric Loops Technique

楊豐睿(Fong-Jui Yang)

指導教授 ： 陳中平

共同指導教授 ： 趙昌博(Cheong-Po Chao)

國立臺灣大學/電機資訊學院/電子工程學研究所/碩士(2021年)

https://doi.org/10.6342/NTU202100903

摘要

本論文為一個採用對稱性迴路之閘式壓控震盪器突發式時脈資料回復電路。在現今高速骨幹網路中，如SONET/OTN、10GbE、100GbE、LANS和PON，在寬頻網路中扮演重要的角色。為了實現這種系統，必須提供高速低功率的通訊積體電路。對於高速接入網路中使用的資料時脈回復電路，必須提供快速時脈回復與瞬時鎖相，並且維持較低的抖動產生。
本篇的突發式資料時脈回復電路是針對閘式壓控震盪器去做改良。本篇將傳統雙迴路的閘式壓控震盪器合併為一個對稱性結構的電路，解決了兩個閘式壓控震盪獨立運作產生的時脈扭曲問題，並且降低了邏輯閘數目和不需使用到特定時間的延遲電路。透過該突發式資料時脈回復電路，可以在資料輸入後的一個位元資料週期內完成相位鎖定，且產生較低的抖動。此外，本論文也使用到次取樣鎖相迴路去做鎖頻，當參考訊號和除頻器輸出訊號相位差小於180度時，迴路會關閉增益較低的相位/頻率偵測器，改由較高增益的次取樣相位偵測路徑來降低其他電路所產生的雜訊，進而降低資料時脈回復電路的抖動產生。
本晶片使用台積電90奈米互補式金氧半製程，主動面積約為0.822mmx0.829mm2，在電源供應1V下，突發式資料時脈回復電路的還原 RMS 時脈抖動產生為3.68ps，鎖定時間為一個位元週期，功耗為6.9mW;次取樣鎖相迴路輸出為3.125GHz，參考突波為-52.23dBc，在偏移輸出頻率1MHz的相位雜為-93.57dBc/Hz，功耗為6.47mW。

關鍵字

被動光纖網路 ； 突發式資料時脈回復電路 ； 鎖相迴路 ； 次取樣 ； 閘式壓控震盪器

並列摘要

This thesis presents a burst-mode CDR using a GVCO with symmetric loops technique. In today's high-speed links used in backbone networks, such as SONET/OTN, 10 GbE, 100 GbE, LANS and PON, play an important role in broadband networks. In order to realize this kind of system, we must provide the high-speed and low-power communication integrated circuit. For the clock and data recovery (CDR) circuit used in high-speed access networks, it is essential to provide a fast clock extraction with the instantaneous phase locking. For CDR used in high-speed access networks, a fast phase locking time and low jitter generation must be provided.
This burst-mode CDR is designed to improve gated-VCO. This thesis merges the traditional dual loops gated-VCO into a symmetrical structure circuit, which solves the distortion of signals and unstable operation caused by the independent operation of two GVCOs. It also reduces the number of logic gates and precise delay cell is not needed. Through this circuit, phase locking can be completed in one data period and low jitter is generated. In addition, this paper also uses the sub-sampling phase-locked loop to lock the frequency, when the output frequency is locked and the phase difference between reference and divider output is less than 180°, the frequency-locked loop is turned off and sub-sampling phase detector with higher gain dedicates on phase locking to reduce the noise generated by other circuits.
This chip is fabricated in TSMC 90nm CMOS technology with an active area of 0.822mm x 0.829mm^2. The RMS jitter generation from burst-mode CDR is 3.68ps and locking time is one data period under 1V power supply with 6.9mW power dissipation. The sub-sampling phase-locked loop output frequency is 3.125GHz. The reference spur is -52.23dBc/Hz and phase noise is -93.57dBc/Hz at 1MHz offset from carrier frequency with 6.47mW power dissipation.

並列關鍵字

Passive optical network ； Burst-mode CDR ； Phase-locked loop ； Sub-sampling ； Gated-VCO

參考文獻

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