用於保護電驛之直流偏移消除技術數位積體電路設計

Digital Integrated Circuit Design of DC-offset Removal Scheme for Protective Relay

洪培倫(Pei-Lun Hong)

指導教授 ： 劉志文

國立臺灣大學/電機資訊學院/電機工程學研究所/碩士(2004年)

https://doi.org/10.6342/NTU.2004.00766

摘要

本論文主要目的是將直流偏移消除技術實現於晶片設計上，並利用FPGA來對此電路進行實體上之驗證，以說明此電路之可行性。本文採用Bottom-Up之設計方式，將此直流偏移消除技術分成三個模組，對於第一個FCDFT(Full Cycle Discrete Fourier Transformation)模組之設計，使用管線(Pipeline)之設計觀念；而對於第二個複數運算處理模組，提出了一個「多重正規化」之設計技巧以提升模組之運算精準度；最後的CORDIC模組，使用CORDIC演算法來進行直角座標與極座標之轉換。此電路對於基頻相量之振幅大小誤差率約為1.6~1.9%，而對於相角之誤差率約介於0.005~0.05%。
若使用TSMC所提供的0.35um製程對此電路進行合成，晶片面積約為33242μ㎡，而最高工作頻率可達65.32MHz。若使用Altera公司的Stratix系列中的EP1S25F780C5晶片來實現此電路，約使用18%的邏輯元件，87%的DSP元件，與9%的輸出腳位，且其最高工作頻率可達6.13MHz。

關鍵字

全週期傅利葉轉換 ； 座標旋轉數位運算演算法 ； 複數運算

並列摘要

In this thesis, we design a chip to implement DC-offset removal scheme, and then we use FPGA to verify the function of our circuit for proving its availability. By Bottom-Up design style, we divide this system to three parts. First part is FCDFT module, and we adopt Pipeline concept to accomplish it. Second part is complex number computing module, and we develop a “re-normalization” scheme to improve precision. Last part is CORDIC module, and we use it for transferring rectangular coordinate to polar coordinate. About its result, the error rate of baseband amplitude is 1.6~1.9%, phase angle 0.005~0.05%.
If we adopt TSMC 0.35um technology library to synthesis our design, the area is approximately 33242um2, the maximal frequency is 65.32MHz. If we use Altera Stratix EP1S25F780C5 device to implement our design, it use 19% logic element, 87% DSP block and 9% pins, and its maximal frequency is 6.13MHz.

並列關鍵字

Complex Number Arithmetic ； FCDFT ； CORDIC Algorithm

參考文獻

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