應用於內建自我測試機制之V頻段互補式金氧半導體低雜訊放大器與寬頻射頻功率偵測器之研製

Design and Analysis of V-band CMOS Low Noise Amplifier and Wideband RF Power Detector for Built-in Self-Test Technique

賈士卜(Shyh-Buu Gea)

指導教授 ： 黃天偉

國立臺灣大學/電機資訊學院/電信工程學研究所/碩士(2011年)

https://doi.org/10.6342/NTU.2011.10419

摘要

隨著無線通信應用市場的快速發展，微波頻帶已趨近於飽和，為了能有更寬的頻譜來達成更快的傳輸速率，寬頻的毫米波無線通信系統將被需要。功率檢測器在無線通信系統的自動增益控制迴路（AGC）以及自動功率控制迴路（ALC）中扮演著重要的角色，更能實現電路內建自我測試機制，克服隨著為了整合系統在同一片晶片上而日漸複雜的量測。
本論文主要分為兩個部分，第一部分是射頻均方根功率檢測器的設計與研究，其中包括振幅偵測器、低通濾波器、以及對數放大器，對數放大器使功率偵測器的輸出電壓對於輸入功率呈現線性關係。此功率偵測器的直流功耗為4.9毫瓦，可偵測的線性範圍從-15dBm~10dBm，而穩定時間最快則達到10奈秒。使用90奈米互補式金氧半場效電晶體（CMOS）實現。
第二部分是V頻帶低雜訊放大器的設計與研究，使用三級串接（cascade）共源級放大器。當中利用場效電晶體基級端偏壓技巧，使得該放大器直流功耗可以較一般放大器來的小，電路量測在57GHz~66GHz中都有將近19dB的小訊號增益，模擬的雜訊指數在60GHz~70GHz頻寬中都低於5.7，使用65奈米互補式金氧半場效電晶體（CMOS）實現。
並在其後的章節，展現一個基於上述電路設計原理下的內建自我測試機制，作為內建自我測試機制電路的範例。

關鍵字

功率檢測器 ； 和分貝值線性 ； 自動增益控制 ； 低雜訊放大器 ； 內建自我測試 ； V頻段 ； 互補式金氧半場效電晶體

並列摘要

With the fast growing of the wireless communication market, the microwave frequency bands are not enough for these communication applications. In order to fabricate high-speed and high-data rate communication systems, we need to develop the wideband millimeter-wave communication systems. The power detector is a major component of the automatic gain control circuits and automatic level control circuits in wireless communication systems. Furth more, the power detector can help to accomplish self-test for avoiding the complicated tests in SoC.
This thesis can be divided into two parts. The first part is the design of the RF CMOS RMS power detector using CMOS 90-nm process, which includes amplitude detector, low pass filter and logarithmic amplifier. We utilize the logarithmic amplifier to get a linear-in-decibel output voltage. The input linear dynamic range of the proposed power detector is 25 dB at different frequencies from 1.8 GHz to 60 GHz, and the total DC power consumption is 4.9 mW. The fastest simulated settling time is 10ns. The second part is V-band low noise amplifier using CMOS 65-nm process. We adopt three-stage common source topology in this design. It also utilize body-effect to reduce the DC power consumption of the proposed amplifier. The measured gains are above 19 dB from 57 GHz to 66 GHz, and the simulated noise figures are all lower than 5.7 dB from 60 GHz to 70 GHz.
After discussing these two major components of the built-in self-test techniques, we will also demonstrate an example of a low noise amplifier with built-in self-test techniques.

並列關鍵字

power detector ； linear-in- decibel ； automatic gain control (AGC) ； low noise amplifier (LNA) ； built-in self-test (BIST) ； V-band ； CMOS

參考文獻

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[1] Yen-chih Huang, Hsieh-Hung Hsieh, Liang-Hung Lu, “A Build-in Self-Test Technique for RF Low-Noise Amplifiers,” IEEE Trans. Micro. Theory Tech., vol. 56, no.5, pp. 1035-1042, May 2008.