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  • 學位論文

以射頻磁控濺鍍法製作之氧化鎂鋅/氧化鋅薄膜電晶體特性研究及其於邏輯閘之應用

MgZnO/ZnO Thin-Film Transistors and Logic Gates Fabricated by RF Magnetron Sputtering

指導教授 : 陳奕君

摘要


本論文探討多晶系氧化鎂鋅/氧化鋅異質接面結構特性,並應用於薄膜電晶體及邏輯閘之製作。 實驗使用射頻磁控濺鍍法在室溫下於玻璃基板製作氧化鎂鋅/氧化鋅異質結構。首先,研究不同退火溫度對氧化鋅結晶程度及氧化鎂鋅/氧化鋅異質接面特性之影響。接著將異質結構製作成薄膜電晶體,此部份採用氧化鋁為閘極介電層,確認極化效應能有助於薄膜電晶體特性的提升,其中採用600°C氧化鋅退火溫度之元件有最佳表現,其電流開關比、臨界電壓、次臨界擺幅與場效載子遷移率分別為2.3×105、-2.90 V、0.714 V/decade以及70.2 cm2/V-s。此外,在薄膜電晶體之閘極介電材料研究上,發現氧化鎂的使用能改善介電層與通道層之介面,進而大幅提升薄膜電晶體之場效載子遷移率至132 cm2/V-s。 最後將異質結構薄膜電晶體製作成邏輯反相器電路,著重分析閘極介電層材料對反相器電壓轉換特性之影響,其結果發現相較於使用氧化鋁,使用氧化鎂為閘極介電層之邏輯反相器具有較佳的訊號增益,由6.26上升至12.3,以及相對較小的磁滯現象偏移量,由14.6 V下降至4.79 V。

並列摘要


This thesis reports the experimental results regarding the electronic devices and logic gates based on RF-sputtered MgZnO/ZnO polycrystalline heterostructures. The carriers can be induced by polarization effect at the MgZnO/ZnO interface, forming two dimensional electron gases (2DEGs). This can be confirmed through the enhancement of electrical conductivity after the deposition of MgZnO capping layer. The polycrystalline MgZnO/ZnO heterostructures were RF-sputtered on glass substrates at room temperature. We first investigated the influence of ZnO annealing temperature on the properties of the heterostructures. The formation of 2DEGs was observed in the heterostructures with ZnO annealed at a temperature of 400°C or high. The MgZnO/ZnO heterostructure was then used as the active layer in top-gate thin-film transistors (TFTs) and logic inverters. The best performance was obtained in the TFT with ZnO annealed at 600°C with Al2O3 as the gate dielectric, which has an on/off current ratio of 2.3×105, a threshold voltage of -2.90 V, a subthreshold swing of 0.714 V/decade and a saturation field-effect mobility of 70.2 cm2/V-s. The performance of thin-film transistors is also greatly affected by the dielectrics and the interface properties between the dielectric and channel layers. By replacing Al2O3 with MgO, the better interface between dielectric and channel layer increases the field-effect mobility of heterostructure TFT, which shows an improved mobility of 132 cm2/V-s. Moreover, the logic inverters with MgO gate dielectric exhibit better voltage transfer characteristics (a gain of 12.3) with smaller hysteresis compared to those with Al2O3 gate dielectric (a voltage shift of 4.79 V).

參考文獻


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