使用SAB濾波器與時間數位轉換量化器之連續時間三角積分調變器

Design of a Continuous-Time Delta-Sigma Modulator with Single-Amplifier-Biquad (SAB) Filter and TDC-based Quantizer

魏子安(Tzu-An Wei)

指導教授 ： 林宗賢

國立臺灣大學/電機資訊學院/電子工程學研究所/碩士(2014年)

https://doi.org/10.6342/NTU.2014.01530

摘要

在本論文中提出了一個結合單級運算放大器濾波器架構的低功率連續時間型三角積分調變器，調變器本身將迴路延遲補償的方式利用系統回授到特定節點上來完成補償，同時將此補償的方式應用在雙T型單運算放大器濾波器裡面，其中更利用補償所使用的電阻來幫助迴路做相位補償；量化器方面採用一個低功率的時間數位轉換器的量化器,一般回授數位類比轉換器的不匹配所產生的非線性會使得整體調變器產生不必要的雜訊，導致電路訊號雜訊比會大大的降低，因此本論文採用一個天生就具有動態元件匹配電路的功能時間數位轉換器。
此三角積分調變器使用台積電90奈米互補式金氧半製程所實現，在使用300 MHz的取樣頻率在8.5 MHz的頻寬下可以得到67.2 dB的訊號雜訊比和73 dB的動態範圍，在1.2伏特的供應電源、回授數位類比轉換採用1.4伏特時，只需要消耗4.3毫瓦的功率，且FoM為135 fJ/conv-step。

關鍵字

連續型 ； 三角積分調變器 ； 單一放大器之雙極濾波器 ； 時間領域的量化器

並列摘要

A power-efficient continuous-time delta-sigma modulator (CTDSM) employing a single-amplifier biquad (SAB) based topology is proposed. The modulator incorporates a proposed twin-T SAB topology where the excess loop delay (ELD) is compensated by injecting a feedback signal into an internal node of the SAB while cooperating with an additional phase-compensation resistor. The non-linearity induced by the mismatch of feedback DAC will increase the in-band noise, thus jeopardizing the SNDR. A low-power time-to-digital converter (TDC) with an embedded data-weighted-averaging (DWA) function is proposed as the quantizer, which mitigates the mismatch issue in the feedback DACs.
Fabricated in 90-nm CMOS, the proposed CTDSM achieves peak SNDR of 67.2 dB and dynamic range of 73 dB over an 8.5 MHz signal bandwidth, while consuming 4.3 mW at 300 MHz sampling frequency from a power supply of 1.2 V and a dedicated supply of 1.4 V supply for the feedback DAC, and achieve an FoM of 135 fJ/conv-step.

並列關鍵字

continuous-time ； delta-sigma modulator ； single-amplifier-biquad (SAB) filter ； time-domian quantizer

參考文獻

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