摘要
本論文設計一個低電壓、低成本、寬頻且快速鎖定，且可應用在DVB-H UHF頻段的三階頻率合成器，該頻率合成器被使用在偶次諧波混波器的直接降頻接收器（Direct down-conversion Receiver）上。頻率合成器提供675M∼1275MHz的頻率輸出，在輸出端加入除三電路之後產生225M∼425MHz，這訊號可作為Even-Harmonic Mixer本地震盪的訊號。 以精簡DFF組成的相位頻率檢測器和差動操作的電荷幫浦來提升電路的操作速度，可提高輸入參考頻率的大小，減少系統的鎖定時間；利用四位元的控制訊號來切換MIM電容陣列，可改變電壓控制震盪器的中心頻率，增加電壓控制震盪器的輸出範圍；由控制可程式化的除頻器，可讓我們獲得想要使用的輸出頻率 電路設計採用tsmc 0.18um CMOS Mixed/RF製程，操作電壓為1V。輸入的參考訊號為48MHz，再透過輸入的除頻器決定頻寬大小為8MHz或6MHz，因此再輸出端可得到跳頻為6MHz或8MHz兩種頻寬的輸出。有675M∼1275MHz和225M∼425MHz兩種輸出訊號可以使用，鎖定時間小於20us，功率消耗小於13mW，相位雜訊在1.45MHz偏移時小於-126.28dBc/Hz，晶片大小為1.0605mm2。
並列摘要
A low cost, low voltage, wide-bandwidth and fast-locking of 3rd frequency synthesizer is designed. The single voltage-controlled oscillator (VCO) covered the frequency from 675 MHz to 1275 MHz. The divide-by-three prescaler is integrated on chip to provide the I/Q signals from 225 MHz to 425 MHz, and the outputs can be used as the LO of the UHF TV even-harmonic direct down-conversion. The differential control help to shorten the response time of the charge pump. And, the propagation delay of the D flip-flops is reduced to facilitate high reference clock of phase frequency detector. The dead zone issue does not exist in this design. The frequency divider architecture is pulse-swallow counter. By controlled program counter and swallow counter, frequency divider operation range is between 2 to 192. The frequency synthesizer was implemented in TSMC CMOS 0.18um 1P6M technology. The die size is 1.05×1.01 mm2. The supply voltage of the frequency synthesizer is 1V and the power consumption is 13 mW. The measured phase noise is -127.28 dBc/Hz at 1.45MHz offset from carrier.