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  • 學位論文

使用新穎辭典並考慮實體資訊之多重缺陷診斷

Multiple Defect Physical-aware Diagnosis using Novel Dictionary

指導教授 : 李建模

摘要


這篇論文針對多重缺陷的錯誤晶片提出一個考慮實體資訊並使用新穎辭典的診斷技術,我們的技術同時考慮錯誤遮蔽/增強效應以及拜占庭效應。我們使用影響單一缺陷有關的導線片段作為診斷的最小單位,然後,我們提出一個導線片段對應實體位置的技術來找出真正的缺陷。在ISCAS’89和ITC’99的電路上,多重導線開路缺陷的實驗顯示出我們診斷技術的能力。當插入的缺陷數量越多,此技術的診斷正確率會越高於商業軟體。當插入10個多重導線開入缺陷時,此技術的正確率(0.67)比商業軟體的正確率(0.31)還高出許多。

並列摘要


This thesis presents a physical-aware diagnosis technique for failing dies with multiple defects using novel dictionary. Our diagnosis technique considers fault masking/reinforcement and Byzantine effects simultaneously. We identify sections that involved in a defect as the smallest diagnosis unit. Then, we propose section to physical site mapping technique to find culprit defects. Simulations on ISCAS’89 and ITC’99 benchmark circuits with multiple open-via defects demonstrate the effectiveness of our diagnosis technique. The accuracy is higher than commercial tool when more defects are injected. The accuracy of MD-PhD with 10 open-via defects injected (0.67) is much higher than commercial tool (0.31).

並列關鍵字

diagnosis multiple defect physical-aware section

參考文獻


[Abramovici 84] M. Abramovici, P.R. Menon, and D.T. Miller, “Critical Path Tracing: An Alternative to Fault Simulation,” IEEE Design & Test of Computers, Vol. 1, pp. 89-93, Feb. 1984.
[Acken 92] J.M. Acken; S.D. Millman, "Fault Model Evolution for Diagnosis: Accuracy vs Precision," in Custom Integrated Circuits Conference, pp.13.4.1, 13.4.4, 1992.
[Bartenstein 01] T. Bartenstein, D. Heaberlin, L. Huisman, and D. Sliwinski, “Diagnosing Combinational Logic Designs Using the Single Location At-a-time (SLAT) Paradigm,” in Proc. of Int’l Test Conf., pp. 287-296, 2001.
[Chen 14] P.-J. Chen, C.-C. Che, H. Jasmine Chao, James C.-M. Li, S.-F. Kuo, P.-Y. Hsueh, C.-Y. Kuo and J.-N. Lee, “Physical-aware Systematic Multiple Defect Diagnosis,” in IET Computers & Digital Techniques, 2014.
[Huang 01] S. Y. Huang, “On Improving the Accuracy of Multiple Defect Diagnosis,” in Proc. of VLSI Test Symposium, pp. 34-39, 2001

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