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  • 學位論文

處理樣式相依的延遲錯誤診斷

Handing Pattern-dependent Delay Faults in Diagnosis

指導教授 : 劉靖家
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摘要


傳統上,診斷的方法是使用靜態模型於延遲缺陷,當存在一種包含穿越電容(cross-couple capacitance)和電阻短路(resistance short)的錯誤因不同的輸入樣本(input pattern)產生在路徑延遲上的不同影響。盲目的利用傳統的診斷方法處理這種錯誤想找出錯誤位置會因為樣式相依的錯誤(pattern-dependent fault)在同一錯誤位置(fault site)有錯誤(faulty)和正確(fault free)兩種現象而導致錯誤的結果。傳統的錯誤診斷方法為分別針對己知的錯誤模型(fault model)提出不同的診斷方法,但實際上當一個電路發生錯誤時 在作錯誤診斷前無法真正得知受何種錯誤模型的影響。而使得只能針各種可能的診斷方法列出可能的錯誤位置,這會造成很大的付出。在這篇論文中,我們提出 處理這些錯誤而無明確的塑造每一種這類的錯誤模型。在我們處理程序中一開始先將我們的問題轉換成線性方程式系統(linear equation system),將每一條所選出的路徑分解為其組成的區段(segment),依每個區段和其訊號視為一個變數。依此方法將所有選到的路徑轉換成線性方程式系統。我們提出的方法。首先第一步驟 利用錯誤路徑的特性將其分成兩個種類 : 靜態的 (static) 和樣本相依 (pattern-dependent),且利用切半(divide)群組方法增加分類的效率。其次將診斷樣本相依路徑問題轉換成診斷靜態路徑問題,利用這兩種不同特性的錯誤路徑我們更進一步的探測這些資訊列出引起錯誤延遲可能的犧牲者(victims)。最後利用不同的錯誤模式(fault model)作為更進一步的分析而找出可能的嫌疑位置。實驗結果顯示出錯誤線段(segment)和連合對(coupling par)嫌疑(suspect)的平均排名分別為2.1和4.6

關鍵字

樣式相依錯誤 診斷

並列摘要


raditionally, diagnosis methods use static models for delay defects, while there exists a class of faults including cross-coupling capacitance and resistive shorts exhibiting different effects on path delays with different input patterns. Blindly treating such faults will lead to skewed results for locating defects. In this paper, we discuss the method to handle these faults without explicitly modeling each type of fault. In the process, we differentiate failed delay paths into two categories: static and pattern-dependent. We further explore these information to list possible candidates (including coupling defects) causing timing failures for further analysis. The experimental results show that average rankings of suspects are 2.1 and 4.6 for failing segments and coupling pairs, respectively. Average ranking represents the average number of candidates need to be checked until find out the injected fault sites on the diagnostic ranking result.

並列關鍵字

pattern-dependent fault diagnosis

參考文獻


[1] Y. Y. Chen, M. P. Kuo, and J. J. Liou, “Diagnosis framework for locating failed segments of
[2] A. Krstic, L. C.Wang, J. J. Liou, and M. S. Abadir, “Diagnosis-based post-silicon timing validation
[3] M. Sivaraman and A. J. Strojwas, “Path delay fault diagnosis and coverage-a metric and an
timing information,” IEEE Transactions on Computer-Aided Design of Integrated Circuits
[5] J. Ghosh-Dastidar and N. A. Touba, “Adaptive techniques for improving delay fault diagnosis,”

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